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長庚大學 綠色科技研究中心
分類清單
馮武雄

馮武雄

教授

 

電話

(03)2118800#5800

Email

fengws@mail.cgu.edu.tw

實驗室

電子構裝實驗室(工學院9E0911)

學歷

  • 國立台灣大學電子電機工程學所 博士 ( 1980/6 )
  • 國立台灣大學電子電機工程學所 碩士 ( 1974/6 )
  • 國立台灣大學電子電機工程學系 學士 (1970/6 )  

經歷

  • 長庚大學 教授兼工學院院長 2001.08~2004.07
  • 長庚大學 教授兼光電工程研究所 所長 2001.08~2003.07
  • 長庚大學 教授兼電子工程學系 主任 1999.03~2005.07
  • 長庚大學 半導體科技研究所(暨電子工程研究所) 所長1999.08~2003.07
  • 美國 約翰.霍普金斯大學(Johms Hopkins Univ.) 兼任 應用物理實驗室(APL) 1994.02.~1994.04
  • 國立台灣大學 電機工程學系 教授 1988.07~1999.03
  • 美國加州大學柏克萊分校 電機電腦系 訪問學者 1984.08~1985.07
  • 國立台灣大學 電機工程學系 副教授 1980.08~1988.06
  • 美國史丹佛大學 電機系 訪問學者 1979.08~1980.07
  • 國立台灣大學 電機工程學系 講師 1974.09~1980.06
  • 林口 電子廠 工程師(高等優等分發) 1974.06~1974.09
  • 大同工學院 電機工程學系 助教 1971.07~1972.08   

開授課程

 
  98學年度第一學期
通訊原理
電路學(1)
射頻積體電路設計
98學年度第二學期:
電路學(2)
混合訊號積體電路設計

專長與研究領域

半導體創新元件的製程與量測

射頻與混合訊號積體電路設計

高頻電路板設計與量測技術研發

奈米超大型積體電路設計與測試

積體電路佈局與演算法

簡歷

Wu-Shiung Feng received the B.S.E.E., M.S.E.E., and Ph.D. degrees fromNational Taiwan UniversityTaipeiTaiwan, ROC, in 1970, 1974, and 1980, respectively. During 1974-1979, he was an Instructor at the Department of Electrical Engineering, National Taiwan University. During 1980 to 1985, he was an Associate Professor, as well as a Full Professor from 1986 to 1998. Since 1998 retired fromNational Taiwan University, he is a Chair of the Department of Electronic Engineering and a Director of Graduate Institute of Semiconductor Technology, Chang GungUniversityTao-YuanTaiwan, ROC. He was the dean of the College of Engineering,Chang Gung University from 2001 to 2004.

       From 1979 to 1980, he was a Visiting Scholar at Stanford UniversityPalo Alto,CA, where he spent one year in Solid-State Electronics Laboratory. From 1984 to 1985, he joined the IC design group at the Department of EECS, University ofCaliforniaBerkeleyCA. His current research interests are VLSI layout, timing and integrity design, and wideband RF IC design. He has published over hundreds of technical papers. He was awarded the Best Technical Paper Award at the Chinese Institute of Engineers, Rep. of China, in 1981 and the Best Paper Award of Design Session, IMAPS Society, May 1998. He obtained the 2001 Academic Excellent Award of Chang Gung University. Dr. Feng is a Senior member of the IEEE Society and the Chinese Institute of Engineers.

著作列表

Journal articles & book chapters:

  1. W. S. Feng, "Design, fabrication, and characteristics of emitter coupled logic integrated circuits," M. S. Thesis, Institute of Electrical Engineering, National Taiwan UniversityTaipeiTaiwan, Rep. of China, June 1974.
  2. W. S. Feng, "The study of liquid-phase epitaxial method for AlGaAs LED," Proceeding of National Science Council, Taipei, Rep. of China, No. 9, Part. 3, p.125, 1976.
  3. S. C. Chang and W. S. Feng, "The study of chemical transport GaAsP on silicon substrates," Engineering Science Research CenterTainanTaiwan, ROC, Research Bulletin, pp.18-1/18-44, Jan. 1977.
  4. W. S. Feng, S. M. Sze, and H. J. Yu, "Liquid-phase epitaxy of (p)AlGaAs-(n)GaAs and electroluminescent devices," Bulletin of the College ofEngineeringNational Taiwan UniversityTaipei, Rep. of China, No. 26, p.75, 1979.
  5. W. S. Feng, S. M. Sze, andH. J. Yu, "GaAlAs heterojunction solar cells with liquid-phase epitaxy," Bulletin of the College of EngineeringNationalTaiwan UniversityTaipei, No. 25, p. 93, 1979.
  6. W. S. Feng, "Anodic oxidation for AlGaAs-GaAs solar cells," Journal of Electrical Engineering, Taipei, Rep. of China, Vol. 23, No. 6, p.84, 1980. (EI)
  7. W. S. Feng, "Growth and properties of AlGaAs-GaAs photoelectric devices prepared by liquid-phase epitaxial techniques," Ph. D. Thesis,National Taiwan UniversityTaipeiTaiwan, Rep. of China, 1980.
  8. W. S. Feng and G. L. Pearson, "Voltage-controlled light-switching diodes," The Institute of Physics, Bristol, London, England, pp. 503-508, 1981. (EI)
  9. W. S. Feng, "(P)AlGaAs-(N)AlGaAs-(n)GaAs voltage-controlled light-switching diodes," Journal of Electrical Engineering, Taipei, Taiwan, Rep. of China, Vol.24, No.1, pp. 30-52, 1981.(EI)
  10. J. C. Yang, H. J. Yu, and W. S. Feng, "An automatic gate-matrix layout generation system," Bulletin of the College of EngineeringNational TaiwanUniversityTaipeiTaiwan, Rep. of China, No.36, pp. 21-37, Sept 1984.
  11. W. S. Feng and H. J. Yu, "An interactive symbolic layout system for Integrated-circuit design-HISLID," CAD/CAM/CAE for Industrial Progress, North-Holland Co., Amsterdam, The Netherlands, pp. 41-50, 1986. (EI)
  12. I. C. Jou, Y. H. Hu, H. J. Yu, and W. S. Feng, "Parallel algorithm and architecture for solving covariance eigen systems," Advances in Modeling and Simulation, France, Vol. 5, No.2, pp. 47-63, 1986. (SCI)
  13. W. S. Feng, T. Y. Chan, and C. Hu, "MOSFET drain breakdown voltage,"IEEE Trans. Electron Device Letters, Vol. EDL-7, No.7, pp. 449-450, July 1986.(SCI)
  14. I. C. Jou, Y. H. Hu, and W. S. Feng, "A novel implementation of pipelined Toeplitz system solver," Proceeding of IEEE, Vol. 74, No. 10, pp.1463-1464, Oct. 1986.(SCI)
  15. P. Y. Hsiao and W. S. Feng, "Using hierarchical multiple storage quad tree on a constraint-graph layout compaction," Journal of the Chinese Institute of Engineers, Taipei, Rep. of China, Vol. 12, No. 3, pp. 301-315, 1989. (EI)
  16. K. E. Chang and W. S. Feng, "Graph contractibility problem for VLSI layer assignment," Journal of the Chinese Institute of Engineers, Taipei, Rep. Of China, Vol. 12, No. 4, pp. 485-495, 1989. (EI)
  17. K. E. Chang, H. F. Jyu, and W. S. Feng, "Constrained via minimization for three-layer routing, " Computer-Aided Design, Butterworth & Co Ltd, London, Vol. 21, No.6, pp.346-354, July/August 1989.(SCI)
  18. P. Y. Hsiao, W. S. Feng, and H. F. Chen, "An application of an expert system in layout compaction of VLSI design," Journal of the Chinese Institute of Engineers, Taipei, Rep. of China, Vol.12, No.4, pp.497-510, 1989. (EI)
  19. P. Y. Hsiao, W. S. Feng, and H. F. Chen, "New algorithms based on multiple storage quadtrees in hierarchical compaction of VLSI mask layout," Computer-aided Design, Butterworth &Co Ltd, London, Vol. 22, No. 2, pp. 74-80, 1990.(SCI)
  20. K. E. Chang and W. S. Feng, "A delayed layering for three-layer channel routing," IEEProceedings, Vol. 137, Pt.E, No.4, pp. 229-238, July 1990.(SCI)
  21. C. C. Tsai, S. J. Chen, and W. S. Feng, "Generalized terminal connectivity problem," Computer-aided Design, Butterworth & Co Ltd, London, Vol. 22, No.7, pp.423-433, September 1990.(SCI)
  22. K. E. Chang, T. H. Lai and W. S. Feng, "A topological sorting algorithm for three-layer channel routing," Journal of the Chinese Institute of Engineers, Taipei, Rep. of China, Vol.13, No.6, pp. 673-683, 1990. (EI)
  23. K. E. Chang and W. S. Feng, "Maximizing pin alignment in VLSI routing with movable terminals," The Journal of the Chinese Institute of Engineers, Vol. 13, No. 1, pp. 103-114, 1990. (EI)
  24. P. Y. Hsiao and W. S. Feng, "Using multiple storage quad tree on a hierarchical VLSI compaction scheme," IEEE Trans. on Computer-Aided Design/ICAS, pp. 522-536, May 1990.(SCI)
  25. C. C. Tsai, S. J. Chen, and W. S. Feng, "An H-V Tile-expansion router,"Journal of Information Science and Engineering, Taipei, Taiwan, Rep. of China, Vol. 6, pp. 173-189, 1990.(SCI)
  26. P. Y. Hsiao, H. F. S. Chen, and W. S. Feng, "A new control strategy for an artificial intelligence approach to VLSI layout compaction," The VLSI Journal of INTEGRATION, Vol.10, No.1, pp. 55-70, 1990.(SCI)
  27. C. C. Tsai, S. J. Chen, P. Y. Hsiao, and W. S. Feng, "A new iterative construction approach to routing with compacted AreaIEE Proceedings-E Computers and Digital Techniques, pp. 57-71, 1991.(SCI)
  28. P. H. Shih and W. S. Feng, "An analog neural network approach to global routing problem," An International Journal on Cybernetics and System, vol. 22, pp. 747-757, 1991.(SCI)
  29. P. H. Shih, W. S. Feng and K. E. Chang, "Neural network approach to routing problem," Journal of the Chinese Institute of Engineers, Vol. 14, No. 3, pp. 295-306, 1991.(EI)
  30. C. C. Tsai, S. J. Chen, P. Y. Hsiao, and W. S. Feng, "Routing area compaction based on iterative constructionJournal of the Chinese Institute of Engineers, Vol. 14, No. 3, pp. 239-256, 1991. (EI)
  31. P. Y. Hsiao, W. S. Feng, C. C. Tsai and H. F. Chen, "A knowledge-based program for compacting the mask layout of integrated circuits," Int. Journal of Computer-aided Design, vol. 23, No.3, pp.223-231, 1991.(SCI)
  32. P. H. Shih, K. E. Chang and W. S. Feng, "A neural computation network for global routing,Computer-Aided Design, Vol. 23, No. 8, pp. 539-547, Oct. 1991.(SCI)
  33. P. H. Shih and W. S. Feng, "An application of neural network on channel routing problem," Parallel Computing, vol. 17, pp. 229-240, 1991.(SCI)
  34. P. H. Shih and W. S. Feng, "Channel routing using neural networking,"Journal of the Chinese Institute of Engineers, vol.14, No. 6, pp.603-610, 1991. (EI)
  35. H. C. Chow and W. S. Feng, "Analytical delay model of CMOS inverter including channel-length modulation," Electronics Letters, Vol. 28, No.4, pp. 408-410, 1992.(SCI)
  36. H. C. Chow and W. S. Feng, "Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification,"Electronics Letters, Vol. 28, No. 12, pp. 1159-1160, 1992.(SCI)
  37. H. C. Chow, W. S. Feng and J. B. Kuo, "Simple analytical model for short-channel MOS devices," IEE proceeding Part G, Vol.139, No. 3, pp.405-409, 1992. (SCI)
  38. C. C. Tsai, S. J. Chen, and W. S. Feng, "An H-V Alternating Router," IEEE Trans. on Computer-Aided Design/ICAS, Vol.11, No.8, pp. 976-991, August 1992. (SCI)
  39. H. C. Chow and W. S. Feng, "An improved analytical model for short-channel MOSFET's," IEEE Trans. Electronic Devices, pp. 2626-2629, Vol.11, Nov. 1992. (SCI)
  40. H. C. Chow and W. S. Feng, "An analytical CMOS inverter delay model including channel-length modulations," IEEE J. Solid- State Circuits, pp. 1303-1306, Sept. 1992. (SCI)
  41. H. C. Chow, W. S. Feng, and J. B. Kuo, "An improved analytical short-channel MOSFET model valid in all regions of operation for analog/digital circuit simulations," IEEE Trans. on Computer-Aided Design/ICAS, Vol. 11, No. 12, pp.1522-1528, 1992. (SCI)
  42. J. H. Wang, M. Chang, and W. S. Feng, "BTS-Binary-tree timing simulator with the considerations of internal charges," IEE Proceedings. E, pp. 211-219, July 1993.(SCI)
  43. J. H. Wang, J. T. Fan and W. S. Feng, "Charge-based current model for CMOS gates," Electronics Letters 22nd, Vol.29, No.15, pp. 1343-1345, July 1993. (SCI)
  44. J. M. Wang, S. C. Fan and W. S. Feng, "New efficient designs for XOR and XNOT functions on transistor level," IEEE Journal of Solid-State Circuits, Vol.29, No.7, pp.780-786, July 1994. (SCI)
  45. J. H. Wang, M. Chang, and W. S. Feng, "A waveform-based gate-level timing simulator (BTS) for MOS VLSI circuits with considerations of the internal charge effects," Journal of the Chinese Institute of Engineers, Vol.18, No.2, pp.147-159,March 1995.(EI)
  46. W. S. Feng, J. H. Wang and J. T. Fan "A current waveform simulator using charge-based current model," Journal of the Chinese Institute of Engineers, Vol.18, No.3, pp.303-312, May 1995.(EI)
  47. C. J. Chen and W. S. Feng, "Relaxation-based transient sensitivity computation for MOSFET circuits," IEEE Trans. CAD of ICAS, Vol.14, No.2, pp.173-185, Feb. 1995.(SCI)
  48. S. C. Fang, J. H. Wang and W. S. Feng, "A new direct design for three-input XOR function on the transistor level," IEEE Trans. on Circuits and Systems, Vol.43, No.4, pp.343-348, 1996.(SCI)
  49. M. -S. Lin, M. -C. Lee, D. Y. Chen and W. S. Feng, "Synchronous dimming control for a cold-cathode fluorescent lamp driver," Electronics Letters, Vol.32, No.13, pp.1151-1153, 1996.(SCI)
  50. S. -J. Yih, M. Cheng and W. S. Feng, "Multilevel barrel shifter for CORDIC design," Electronics Letters, Vol.32, No.13, pp.1178-1179, 1996. (SCI)
  51.  W. -J. Ho, M. S. Lin and W. S. Feng, "Optimizing single-phase PFC-pre-staged AC/DC/AC topology via common-neutral connection,"Electronics Letters, Vol.32, No.17, pp.1529-1530, 1996. (SCI)
  52. J. B. Lio, M. -S. Liu, D. Y. Chen and W. S. Feng, "Single-switch soft-switching flyback converterElectronics Letters, Vol.32, No.16, pp.1429-1430, 1996. (SCI)
  53. M. -S. Lin, J. -B. Lio, D. Y. Chen and W. S. Feng, "Primary-side dimming control driver for cold-cathode fluorescent lamps," Electronics Letters, Vol.32, No.15, pp.1334-1335, 1996. (SCI)
  54. M. Chang, S. J. Yih and W. S. Feng, "Algorithm based on modified threaded binary tree for estimating delay affected by internal charges in CMOS gates," Electronics Letters, Vol.32, No.20, pp.1877-1879,1996.(SCI)
  55. M. Chang, S. J. Yih and W. S. Feng, "Recursive algorithm for calculating effective resistance in RC treeElectronics Letters, Vol.33, No.2, 1997, pp.131-133.(SCI)
  56. W. -J. Ho, J. B. Lio and W. S. Feng, "Economic UPS structure with phase-controlled battery charger and input-power-factor improvement," IEE Proc. Electr. Power Appl., Vol.144, No.4, pp.221-226, July 1997.(SCI)
  57. W. J. Chen and W. S. Feng, "Pattern-based maximal power estimation for VLSI chip design," IEIC Trans. on Fundamental of Electronics, Communications and Computer Sciences, Vol.E80-A, No.11, pp.2300-2307, Nov. 1997.(SCI)
  58. S. –J. Yih, M. Chang, and W. S. Feng, ”Low latency time CORDIC algorithm,” J. of the Chinese Institute of Electrical Engineering, Vol.5, No.2, pp.175-181, 1998.(EI)
  59. M. Chang and W. S. Feng, “A recursive algorithm for estimating the internal charge sharing effect in RC tree circuits,” IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No.5, pp.913-923, May 1998. (SCI=0.346)
  60. M. L. Chang, J. H. Wang, S. J. Yih, and W. S. Feng, "Waveform approximation technique for CMOS gates in the switch-level timing simulator BTS," Journal of the Chinese Institute of Engineers, Vol.21, No.3, pp.255-268, May 1998. (EI)
  61. B. Y. Ma, T. H. Liu, C. G. Chen and W. S. Feng, “Design and implementation of a sensorless switched reluctance drive system,”IEEE Trans. Aerospace and Electronic System, Vol.34, pp.1193-1207, No.4, Oct. 1998. (SCI)
  62. M. Chang, W. –J. Chen, J. H. Wang and W. S. Feng, “An algorithm for estimating bottleneck effect in series-parallel tree circuits,” IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No.11, pp.2400-2406, Nov. 1998. (SCI=0.346)
  63. H. J. Wu and W. S. Feng, “Efficient simulation of switched networks using reduced unification matrix,“ IEEE Trans. Power Electronics, Vol.14, No.3, pp.481-494, May 1999.(SCI)
  64. C. C. Hsu and W. S. Feng, “OTA-C based BIST structure for analog circuits,” IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, Vol. E83-A, No. 4, pp.771-773, April 2000.(SCI)
  65. C. C. Hsu and W. S. Feng, “Testable design of multi-stage OTA-C filter,”IEEE Trans. Instrumentation and Measurement, Vol. 49, No.5 , pp.929-934, Oct. 2000.(SCI)
  66. L. D. Van, S. S. Wang and W. S. Feng, “Design of the lower-error fixed-width multiplier and its application,” IEEE Trans. Circuits Syst. II, Vol.47, No.10, pp.1112-1118, Oct. 2000.(SCI)
  67. C. C. Hsu and W. S. Feng, “Structural generation of current-mode filters using tunable multiple-output OTAs and grounded capacitors,” IEICE Trans. Fundamentals, Vol..E83-A, No.9, Sept. . 2000, pp.1778-1785.(SCI)
  68. C. C. Hsu and W. S. Feng, “Novel Gm-C realizations of nth-order filters,” IEICE Trans. Fundamentals, Vol. E84-A, No.1, Jan. 2001, pp.339-346. (SCI=0.346)
  69. J.-H. Lee, W. S. Feng, T.-C. Juang, and K.-S. Chang-Liao, “Electric property improvement and boron penetration suppression in metal-oxide-Si capacitors by amorphous-Si gate electrode and two-step nitridation,”J. Vac. Sci. Technol. B, Vol. 19, No.3, pp.794-799, May 2001.(SCI)
  70. L. D. Van and W. S. Feng, “An efficient systolic architecture for the DLMS adaptive filter and its applications,” IEEE Trans. Circuits Syst. II, Vol.48, No.4, pp.359-366, April 2001.(SCI)
  71. H. C. Chow and W. S. Feng, “New symmetrical buffer design for VLSI applications,” Int. J. Electronics, Vol. 88, No. 7, pp. 779-787, 2001. (SCI)
  72. C. C. Tang, C. H. Wu, W. S. Feng, and S. I. Liu, “A 2.4 GHz low voltage CMOS down-converter double-balanced mixer, IEICE Trans. Electron., vol. E84-C, no.8, pp. 1084-1091, Aug. 2001. (SCI=0.346)
  73. W. S. Feng, “2.4-GHz active-load low-noise amplifier,” Journal ofShanghai UniversityChina, Vol. 8, Oct. 2002, pp.199-201.(EI)
  74. H. J. Lee, C. C. Chu, and W. S. Feng, “Moment computations of lumped coupled RLC trees with applications to estimating crosstalk noise,”IEICE Trans. Fundamentals of Electronics, Communications, and Computer Sciences, Vol.E86-A, pp.2952-2964, Dec., 2003. (SCI=0.346)
  75. H. J. Lee, C. C. Chu and W. S. Feng, “Crosstalk Noise Estimations of Interconnects for Nanoelectronics,” WSEAS Transactions on Electronics, Vol.1, pp.128-133, Jan. 2004.(EI)
  76. N. C. Chen, P. H. Chang, A. P. Chiu, M. C. Wang, W. S. Feng, G. M. Wu, C. F. Shih and K. S. Liu, “Modified transmission line model and its application to aluminum ohmic contacts with n-type GaN,” Applied Physics Letters, Vol.84, No.14, April 2004, pp.2584-2587.(SCI=3.849)
  77. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng “Beam Space-Time of a MIMO OFDM-based Wireless LAN System for 2-D Spreading Channels” Journal of WSEAS Transactions on Communications, Issue 2, vol. 3, Apr. 2004, pp. 399-412.(EI)
  78. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng “Beam Space-Time of a BER Minimized OFDM Systems With Bezout Precoders” Journal of WSEAS Transactions on Communications, Issue I, vol3. Jan. 2004, pp.241-247.(EI)
  79. Y. –H. Shu, S. Tenqchen, M.-C. Sun, and W.-S. Feng “Two Efficient Pipelined Designs for MIMO Asynchronous Control,” Journal of WSEAS Trans. On Circuit and System, Issue 1, vol.3, Jan. 2004, pp.193-199.(EI)
  80. H. J. Lee, C. C. Chu, and W. S. Feng, “Indirect approach for designing low-order linear-phase IIR filters using the rational Arnoldi method with adaptive orders,” IEICE Trans. Fundamentals (Special Issue on Digital Signal Processing), Vol.E87-A, No.8, pp.2018-2028, Aug. 2004.(SCI=0.346)
  81. H. J. Lee, Ming-Hong Lai, C. C. Chu, and W. S. Feng, “Applications of Tree/Link Partitioning for Moment Computations of General Lumped R(L)C Interconnect Networks with Multiple Resistor Loops,” IEICE Trans. Fundamentals (Special Issue on VLSI Design and CAD Algorithms), Vol.E87-A, No.12, pp. 3281-3292, Dec. 2004. (SCI=0.346)
  82. S. Tenqchen, Y.-H. Shu, M.-C. Sun, W.-S. Feng, and H.-K. Yen “OFDM System for Frequency-Selective Radio Channel with Maximum Time-Delay Estimation”, Journal of WSEAS Trans. On Circuit and System, Issue 10, vol.3, pp.3133-3138, Dec. 2004.(EI)
  83. M. C. Sun, Y. H. Shu, S. Tenqchen and W. S. Feng, “A one-step input matching method for cascade CMOS low-noise amplifiers,” IEICE Trans. on Electronics, vol.E88-C, no.3, pp.420-428, Mar. 2005.(SCI=0.54)
  84. C. C. Chu, H. J. Lee, and W. S. Feng, “Error estimation of Arnoldi-based interconnect model-order reductions,“ IEICE Trans. on Fundamentals, , vol.E88-A, no.2, pp.533-537, Feb. 2005. (SCI=0.346)
  85. H. J. Lee, C. C. Chu, M. H. Lai, and W. S. Feng, “Moment computations of distributed coupled RLC interconnects with applications to estimating crosstalk noise,” IEICE Trans. Electronics, Vol.E88-C, No.6, pp.1186-1195, Jun 2005.(SCI= 0.346)
  86. Shing TenqChen, Ying-Haw Shu, Ming-Chang Sun, Wu-Shiung Feng and Chao-Hao Lee, ”Performance comparison of PPM-TH, PAM-TH, and PAM-DS UWB rake receivers with channel estimators via correlation mask,”WSEAS Trans. on COMMUNICATIONS, Issue 9, Vol. 4, pp. 751-756, September 2005.(EI)
  87. C. C. Chu, M, H. Lai and W. S. Feng, “Perturbation approach for order selections of two-sided oblique projection-based interconnect reductions,“ IEICE Trans. on Fundamentals, Vol.E88-A, no.12, pp.3573-3576, Dec. 2005. (SCI=0.346)
  88. Wen-Cheng Lai and Wu-Shiung Feng, “5.7GHz CMOS Variable Power Amplifier for Medical Diagnosis Application,” Mingchi Institute ofTechnology Journal, Vo./37.1, pp.33-40, June 2005.
  89. Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, and Wu-Shiung Feng, “XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines,” IEEE Trans. on CAS-II, Vol.53, No.2, pp.138-142, Feb. 2006. (SCI=0.420)
  90. C. C. Chu, H. J. Lee, M, H. Lai and W. S. Feng, “An Adjoint Network Approach for RLCG Interconnect Model Order Reductions,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.2, pp.439-447, Feb. 2006.
  91. C. C. Chu, M, H. Lai and W. S. Feng, “MIMO Interconnects Order Reductions by Using the MultiplePoint Adaptive-Order Rational Global Arnoldi Algorithm,” IEICE Trans. ELECTRON., Vol. E89–C, No. 6, pp.792-802, June 2006. (SCI=0.346)
  92. H. J. Lee, C. C. Chu, and W. S. Feng, “An adaptive-order rational Arnoldi method for model-order reductions of linear time-invariant systems,” Linear Algebra and its Applications, Vol.415, pp.235–261, Jun. 2006. (SCI=0.656)
  93. C. C. Wei, H. C. Chiu and W. S. Feng, “High-linearity performance of 0.13-μm CMOS devices using field-plate technology,” IEEE Electron Device Letters, Vol.27, No.10, pp.843-845, Oct. 2006.(SCI= 2.716)
  94. C. C. Chu, M, H. Lai and W. S. Feng, “The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Output Interconnect Order Reductions,“ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.10, pp.2706-2716, Oct. 2006. (SCI=0.346)
  95. Y. –H. Shu, S. Tenqchen, M. –C. Sun and W. S. Feng, “A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems,” Journal of Information Science and Engineering, Vol. 22 No.4, pp.941-952, July 2006.(EI)
  96. G. M. Wu, C. W. Tsai, C. F. Shih, N. C. Chen, W. S. Feng, 2005, “GaN/Si(111) epilayer based on low temperature AlN and AlGaN/GaN superlattice for light emitting diodes,” Solid State Phenom, Vols. 121-123, pp.587-590, Feb. 2007. (SCI=0.461)
  97. C. C. Chu, M. H. Lai, and W. S. Feng, “Lyapunov-based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.2, pp.415-418, Feb. 2007. (SCI=0.346)
  98. M. H. Lai, C. C. Chu, and W. S. Feng, “On the Equivalent of Structure Preserving Recuctions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.2, pp.411-414, Feb. 2007.(SCI=0.346)
  99. Chien-Cheng Wei, Hsien-Chin Chiu, and Wu-Shiung Feng, “A Low Noise 3.1-10.6 GHz pMOS Distributed Amplifier for Ultra-wideband Applications,” Microwave and Optical Technology Letters, Vol. 49, No. 7, pp. 1641-1644, July 2007. (SCI=0.568)
  100. C. N. Chen, G. M. Wu, and W. S. Feng, “Aligned Polycrystalline Silicon Array Thin Film by XeCl Excimer Laser Annealing for AMOLED Displays,“ Solid State Phenomena, Vol. 124-126, pp. 371-374, 2007. (SCI=0.461)
  101. Chien-Cheng Wei, Hsien-Chin Chiu, , and Wu-Shiung Feng, “A 12-GHz Low-Phase-Noise Voltage-Controlled Oscillator Using Novel Field-Plate CMOS Transistors”, IEEE Trans. on Electron Devices, Vol. 54, No. 10, pp.2803 - 2807, Oct. 2007.
  102. M. H. Lai, C. C. Chu, W.S. Feng, C. F. Shen (2007), “Applications of the Adaptive-Order Global Lanczos Method for MIMO Interconnect Order Reductions”, International Journal of Electrical Engineering, VLSI Special Issue, vol. 14, no. 3, pp. 207-217, June, 2007. (EI)
  103. Chien-Cheng Wei, Hsien-Chin Chiu and Wu-Shiung Feng, “An Improved BS1M4 Model for 0.13-um RF CMOS Using a Simple Lossy Substrate Extraction Method” Microwave Journal, Vol. 51, No. 5, pp. 170-174, May 2008. (SCI=0.191)
  104. Chien-Cheng Wei, Hsien-Chin Chiu, Yi-Tzu Yang, Jeffrey S. Fu and Wu-Shiung Feng, “A UWB CMOS Voltage-Controlled Oscillator with 2-6GHz Tuning-Range Using Active Inductor Technology,” Microwave and Optical Technology Letters, Vol. 50, No.9, pp.2311-2315, Aug. 2008. (SCI=0.631)
  105. C. N. Chen, G. M. Wu*, W. S. Feng and H. W. Jean, “Direct patterning of silicon nitride thin film by projection photoablation for fabricating thin-film-transistor liquid crystal displays,” Japanese Journal of Applied Physics, Vol. 47, No. 4, pp.2152-2154, Apr. 2008. (SCI=1.222)
  106. C. C. Chu, M. H. Lai, and W.S. Feng (2008), “Model-Order Reductions for MIMO Systems Using Global Krylov Subspace Methods”, Mathematics and Computer in Simulations, vol. 79(4), pp.1153-1164, Dec., 2008. (SCI)
  107. Wu-Shiung Feng, Chien-Cheng Wei, Hui-Chen Hsu, Chia-Hsun Chen, and Ling Kung, “ A 3.1 - 30.1GHz Improved Distributed Amplifier in 0.18μm CMOS Technology,” IEEE Microwave and Wireless Components Letters .(submitted)

 

Conference & proceeding papers:

1. W. S. Feng, "Photovoltaic effect of GaAsP," Journal of Electrical Engineering,Taipei, Rep. of China, p.21 (Bulletin), Nov. 1976.

2. W. S. Feng, "The study and fabrication of AlGaAs laser with liquid-phase epitaxy," The 3rd Conference on Semiconductor Devices and Materials, Taipei, Rep. of China, Vol. 3, p. 120, June 1977.

3. W. S. Feng, S. M. Sze, H. J. Yu, and H. H. Jeng, "Liquid-phase epitaxy of (p)AlGaAs-(n)GaAs and electroluminescent device," 1978 Symposium on Electric Materials, Devices, and Circuits, Taipei, Rep. of China, p. B58, 1978.

4. W. S. Feng, S. M. Sze, and H. J. Yu, "GaAlAs heterojunction solar cells,"1978 Symposium on Electric Materials, Devices, and Circuits, Taipei, Rep. of China, p. B63, 1978.

5. W. S. Feng, "Voltage-controlled light-switching diodes," 1980 1st Symposium on Electric Power Proceeding, TainanTaiwan, Rep. of China, p.153, 1980.

6. W. S. Feng and G. L. Pearson, "Voltage-controlled light-switching (VCLS) diodes," International Conference on GaAs and Related Compounds, Osio, Japan, Dec. 1980.(EI)

7. W. S. Feng, "Spectral response of constant and graded bandgap AlGaAs-GaAs solar cells," 1981 Electronic Devices and Materials Symposium, Hsinchu,Taiwan, Rep. of China, pp.159-165, 1981.

8. W. S. Feng, "On-line anodized antireflection coating of graded composition AlGaAs-GaAs solar cells," 1981 Proceedings of International Optoelectronics Workshop, Tainan, Taiwan, Rep. of China, pp. 259-268, 1982.

9. W. S. Feng and P. H. Cheng, "The heteroepitaxial growth of Ge on Si and GaAs on Ge," 1982 Proceedings of Electronic Devices and Materials Symposium,TainanTaiwan, Rep. of China, p.148, 1982.

10. W. S. Feng and S. L. Chang, "Investigation of AlAs deposited by E-gun on GaAs," 1982 Proceedings of Electronic Devices and Materials Symposium, Tainan,Taiwan, Rep. of China, p.123, 1982.

11. W. S. Feng and Y. Y. Shen, " Hydrogen-sensitive Pd-gate MOS transistor," 1982 Proceedings of Electronic Devices and Materials Symposium,TainanTaiwan, Rep. of China, p.122, 1982.

12. W. S. Feng and C. F. Young, "Assigning wires for multilayer routing,"1983 Proceedings of Electronic Devices and Material Symposium, Taipei, Taiwan, Rep. of China, p.226-236, 1983.

13. W. S. Feng, "Heteroepitaxial growth of GaAs/Ge/Si," 1983 Proceedings of Electronic Devices and Materials Symposium, Taipei, Taiwan, Rep. of China, p. 323-330, 1983.

14. W. S. Feng, H. J. Yu, and P. H. Shih, "Cell-based symbolic layout system,"Proceedings of 2nd Japan-ROC Seminar on Computer Aided Design Methodology for VLSI, Tokyo, Japan, pp.63-78, 1984.

15. S. J. Chen, W. S. Feng, M. C. Shi, S. S. Jan, and J. P. Fan, "Design and implementation of a net-list driven layout system," Proceedings of 1985 ROC Electron Devices and Materials Symposium, Hsinchu, Taiwan, Rep. of China, pp. 173-176, Sept. 1985.

16. W. S. Feng and H. J. Yu, "An interactive symbolic layout system for Integrated-circuit design," International Conference on CAD/CAM/CAE,BangaloreIndia, June 1985.(EI)

17. I. C. Jou, Y. H. Hu, H. J. Yu, and W. S. Feng, "Highly concurrent algorithm and pipelined VLSI architecture for solving covariance systems," Proc. Intern. AMSE Conf. on "Modelling & Simulation" Storrs (ConnecticutUSA), July 1-3, pp. 87-103, 1985.(EI)

18. H. H. Yao, W. S. Feng, T. M. Parng, and H. J. Yu, "A routing tool,"Proceedings of 1985 ROC Electron Devices and Materials Symposium, Hsinchu, Taiwan, Rep. of China, pp. 157-160, Sept. 1985.

19. K. T. Tran, T. M. Parng, H. J. Yu, W. S. Feng, C. L. Tyan, and H. C. Ou, "The design and implementation of a mixed-level logic simulator," Proceedings of 1985 ROC Electron Devices and Materials Symposium, Hsinchu, Taiwan, Rep. of China, pp.137-140, Sept. 1985.

20. P. C. Chu, L. F. Sun, T. M. Parng, H. J. Yu, and W. S. Feng," Design and implementation of a data path synthesizer for digital system," Proceedings of 1985 ROC Electron Devices and Materials Symposium, Hsinchu, Taiwan, Rep. of China, pp. 145-148, Sept. 1985.

21. W. S. Feng, "Integrated VLSI Design System: Layout system," CAD/VLSI Workshop, NantouTaiwan, Rep. of China, pp. 68-72, Aug. 1986.

22. W. S. Feng, "The growth and characteristics of GaAs/Ge/Si materials,"1986 Proceedings of Silicon Materials Research Symposium, Hsinchu, Taiwan, Rep. of China, pp. 86-89, Nov. 28, 1986.

23. C. Y. Tyan, W. S. Feng, H. J. Yu, and T. S. Yeh, "Hierarchical timing verification system for multiple clocked logic circuit," Proceedings of 1986 Electron Devices and Materials Symposium, Tainan, Taiwan, Rep. of China, pp. 78 - 83, August 1986.

24. C. C. Tsai, S. T. Kuo, T. C. Uang, L. J. Wang, K. H. Yeap, and W. S. Feng, "Hierarchical layout system," 1987 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, Rep. of China, pp. 292-296, May 1987.

25. K. E. Chang and W. S. Feng, "Top-down placement for hierarchical layout system," Proceedings of 1986 Electron Devices and Materials Symposium, Tainan,Taiwan, Rep. of China, pp.51-56, August 1986.

26. W. S. Feng, "Integrated VLSI Design System: Design entry system,"CAD/VLSI Workshop, NantouTaiwan, Rep. of China, pp.60-61, Aug. 1986.

27. C. I. Wang, W. S. Feng, and T. M. Parng, "Schematic layout editor," Proc. of 1986 Electron Devices and Materials Symposium, Tainan, Taiwan, Rep. of China, pp. 45-50, August 1986.

28. H. C. Ou, W. S. Feng, and H. T. Liaw, "Test sequence generator,"Proceedings of 1986 Electron Devices and Materials Symposium, Tainan, Taiwan, Rep. of China, pp. 84-89, August 1986.

29. S. S. Jan, C. C. Tsai, and W. S. Feng, "LED- A net-list driven layout editor," Proceedings of 1986 Electron Devices and Materials Symposium, Tainan, Taiwan, Rep. of China, pp. 39-44, August 1986.

30. W. S. Feng, "OFF-state MOSFET's breakdown," Proceedings of 1986 Electron Devices and Materials Symposium, Tainan, Taiwan, Rep. of China, pp. 110-115, August 1986.

31. W. S. Feng, "Integrated VLSI Design System: Layout system," CAD/VLSI Workshop, NantouTaiwan, Rep. of China, pp. 60-61, Aug. 1986.

32. Y. C. Yuan, W. S. Feng, and T. M. Parng, "Integrated entry and verification system," Proceedings of International Computer Symposium 1986,TainanTaiwan, Rep. of China, pp.1730-1736, Dec. 1986.

33. I. C. Jou, Y. H. Hu, and W. S. Feng, "Lattice filter array implementation of pipelined Toeplitz system solver," 1986 IEEE International Symposium on Circuits and Systems, San Jose, CA, U.S.A., pp. 235-238, May 1986. (EI)

34. L. F. Sun, T. M. Parng, and W. S. Feng, "Data path modeling and synthesizing for digital systems," Proceedings of International AMSE Conf. "Modeling & Simulation" Williamsburg, Virginia, U. S. A., Vol. 2, pp. 110-129, Sept. 3-5, 1986.(EI)

35. P. Y. Hsiao and W. S. Feng, "The multiple storage quad-tree in constraint-graph compaction of VLSI layout," 1987 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, Rep. of China, pp. 297-301, May 1987.

36. W. S. Feng, K. S. Lee, and H. Tu, "Multi-level hierarchical function simulation," 1987 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, Rep. of China, pp. 129-133, May 1987.

37. C. C. Tsai and W. S. Feng, "HILAS - Hierarchical Interactive layout system," Proceedings of 1987 Electron Devices and Materials Symposium, Taipei, Taiwan, Rep. of China, pp. 303-308, Sept. 1987.

38. J. Y. Chen, C. S. Wang, J. N. Tseng, and W. S. Feng, "Placement and routing with power/ground," 1987 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, Rep. of China, pp. 285-290, May 1987.

39. P. Y. Hsiao and W. S. Feng, "With multiple storage quad tree on the constraint graph compaction of the VLSI large-cell layout-editor,"Proceedings of the 1987 Workshop on Computer Vision, Graphics and Image Processing, Nantou, Taiwan, Rep. of China, Aug. 27, 1987, pp. 12:1-21.

40. S. T. Kuop and W. S. Feng, "Two-layer corner-stitching for interactive routing and pushing of schematic editor," Proceedings of 1987 Electron Devices and Materials Symposium, Taipei, Taiwan, Rep. of China, pp. 315-319, Sept. 1987.

41. N. S. Maa and W. S. Feng, "FAMI: A fast logic minimizer for PLA design,"Proceedings of 1987 Electron Devices and Material Symposium, TaipeiTaiwan, Rep. of China, pp.280-284, Sept. 1987.

42. J. Y. Chen and W. S. Feng, "Automatic floorplan and placement for Hierarchical layout system," Proceedings of 1987 Electron Devices and Materials Symposium, Taipei, Taiwan, Rep. of China, pp. 285-290, Sept. 1987.

43. K. F. Yeh and W. S. Feng, "Extraction and modeling of VLSI cell layout,"Proceedings of 1987 Electron Devices and Materials Symposium, TaipeiTaiwan, Rep. of China, pp.297-302, Sept. 1987.

44. T. H. Chen, W. S. Feng, and C. S. Lin, "A fault grader," Proceedings of 1987 Electron Devices and Materials Symposium, Taipei, Taiwan, Rep. of China, pp. 320-325, Sept. 1987.

45. K. E. Chang and W. S. Feng, "A new dynamic switch-box router,"Proceedings of National Computer Symposium 1987, Taipei, Taiwan, Rep. of China, pp. 471-480, Dec. 17, 1987.

46. P. Y. Hsiao and W. S. Feng, "An edge-oriented compaction scheme based on multiple storage quad tree," The 1988 IEEE International Symposium on Circuits and Systems, Finland, June 6, pp. 2435-2438, 1988. (EI)

47. P. Y. Hsiao, C. Y. Syau, W. S. Feng, T. M. Parng, and C. C. Hsu," A rule-based compactor for VLSI/CAD mask layout," COMPSAC'88: The Twelfth Annual International Computer Software & Applications Conf., Chicago, Illinois, U.S.A., October 5, pp.35-42, 1988. (EI)

48. P. Y. Hsiao and W. S. Feng, "A rule-based expert system for VLSI layout compaction," IECON'88: 14th Annual Conf. of IEEE Industrial Electronics Society, Hyatt Regency, Singapore, Oct. 25, pp.110-115, 1988. (EI)

49. P. Y. Hsiao and W. S. Feng, "An incremental design rule checking based on quad-tree representations," ISMM International Symposium MINI and MICROCOMPUTERS, Florida, Dec. 14, 1988.

50. H. F. Jyu and W. S. Feng, "A global approach for via minimization," Proc. Of International Computer Symposium, Taipei, Rep. of China, pp. 1117-1122, 1988.

51. K. E. Chang, T. H. Lai, and W. S. Feng, "The topological order Determination for three-layer channel routing problem," Proc. of International Computer Symposium, Taipei, Rep. of China, pp. 1129-1134, 1988.

52. P. Y. Hsiao, S. F. Steven Chen, and W. S. Feng, "A heuristic scanning line approach for an expert layout compactor," The IFIP VLSI'89 Conference,Singapore, 1989. (EI)

53. S. F. Steven Chen, P. Y. Hsiao, W. S. Feng, W. T. Wang, and S. N. Dai, "The control model for a knowledge-based approach to VLSI compaction design,Int. Federation for Information Processing, 11th World Computer Congress, San Francisco, CA, USA, pp. 241-246, Aug. 1989. (EI)

54. P. Y. Hsiao, H. F. Chen, W. S. Feng, S. J. Chen, and C. C. Tsai "An improved control strategy for expert compaction design," Proc. of the IASTED International Symposium EXPERT SYSTEMS THEORY & APPLICATIONS, Zurich, Switzerland, pp. 220-223, June 26-28, 1989. (EI)

55. C. C. Tsai, W. S. Feng, S. J. Chen, P. Y. Hsiao, and H. F. Chen "Generalized terminal connectivity problem for multi layer layout scheme," Proc. of the JTC-CSCC'89: Conference on Circuits/Systems, Computers and Communications, Sapporo, Japan, pp. 173-178, June 25-27, 1989. (EI)

56. K. E. Chang, S. C. Fang, and W. S. Feng, "An efficient layer assignment for three-layer restrictive VLSI routing," Proc. of Electron Devices and Materials Symposium, Hsinchu, Taiwan, Rep. of China, pp. 388-397, 1989.

57. C. C. Tsai, S. J. Chen, and W. S. Feng, "An H-V tile-expansion Router,"Proc. of National Computer Symposium, Taipei, Taiwan, Rep. of China, pp. 106-114, Dec. 21 1989.

58. K. E. Chang, C. M. Fu, and W. S. Feng, "The pin alignment in VLSI routing with movable terminals," Proc. of National Computer Symposium, Taipei,Taiwan, Rep. of China, pp.418-424, Dec. 21 1989

59. S. C. Fang, K. E. Chang, and W. S. Feng, "Via minimization with associated constraints in three-layer routing problem," 1990 International Symposium on Circuits and Systems, pp.1632-1635, New Orleans, Louisiana, U.S.A., May 1-3, 1990. (EI)

60. H. C. Chow, J. H. Wang, J. B. Kuo and W. S. Feng, "An improved analytical model of short channel MOSFETs suitable for circuit simulation," 2nd Workshop on CAD for VLSI, Nantou, Taiwan, R. O. C., March 17, 1990, part 1-3, pp.1-6.

61. S. C. Fang, S. J. Chen, and W. S. Feng, "Routing techniques in staircase channels," 2nd Workshop on CAD for VLSI, Nantou, Taiwan, R. O. C., March 17, 1990, part 2-2, pp.1-6.

62. P. H. Shih and W. S. Feng, "Neural computation for VLSI global routing,"2nd Workshop on CAD for VLSI, Nantou, Taiwan, R. O. C., March 17, 1990, part 2-3, pp.1 - 7.

63. C. C. Tsai, S. J. Chen, and W. S. Feng, "An alternating router for compacted routing area," 2nd Workshop on CAD for VLSI, Nantou, Taiwan, R. O. C., March 17, 1990, part 3-2, pp.1 - 9.

64. H. F. Chen, P. Y. Hsiao, W. S. Feng, and S. J. Chen, "A new method for two-dimensional VLSI layout compaction design," 2nd Workshop on CAD for VLSI, Nantou, Taiwan, R. O. C., March 17, 1990, part 3-3, pp.1 - 8.

65. P. H. Shih and W. S. Feng, "Optimal aspect ratios of building blocks for generally structured VLSI floorplan design," 2nd Workshop on CAD for VLSI, Nantou, Taiwan, R.O.C., March 17, 1990, part 5-1, pp.1 - 7.

66. P. H. Shih and W. S. Feng, "Neural computation for global routing,"Proceedings of the IASTED: international Symposium on Modeling, Simulation, and Optimization, Montreal, Canada, pp. 177-181, May 22-24, 1990. (EI)

67. P. H. Shih and W. S. Feng, "Optimal aspect ratios of building blocks for floorplan designs," Proceedings of the IASTED: international Symposium on Modeling, Simulation, and Optimization, Montreal, Canada, pp. 190-194, May 22-24, 1990. (EI)

68. P. H. Shih and W. S. Feng, "Optimal aspect ratios of building blocks for generally structured VLSI floorplan designs, "International symposium on Artificial Intelligence Applications and Neural Networks, ZurichSwitzerland, June 1990. (EI)

69. P. H. Shih and W. S. Feng, "Neural computation for VLSI global routing,"International symposium on Artificial Intelligence Applications and Neural Networks, Zurich, Switzerland, June 1990. (EI)

70. S. C. Fang, K. E. Chang, and W. S. Feng, "A new hybrid sense algorithm for three-layer via minimization with practical constraints," Proceedings of International Computer Symposium, December 1990, Hsinchu, Taiwan, Rep. of China, pp. 583-589.

71. P. H. Shih and W. S. Feng, "A neural network for channel routing," The Fourth CSI/IEEE International Symposium on VLSI Design, New Delhi, India, January 1991. (EI)

72. P. H. Shih and W. S. Feng, "A general-purpose Hopfield network simulator, "The ninth IASTED International symposium on Applied Informatics,InnsbruckAustria, Feb. 18-21, 1991. (EI)

73. C. J. Chen, W. S. Feng, "Transient sensitivity computation in timing simulation," 1991 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, Rep. of China, May 22, 1991,

74. C. C. Tsai, S. J. Chen, P. Y. Hsiao, and W. S. Feng, " Hybrid routing on multichip modules,IEEE Custom Integrated Circuits Conference, San Diego, CA, USA, May 12, 1991, pp.28.4.1-28.4.4. (EI)

75. P. H. Shih, K. E. Chang, and W. S. Feng, " A neural network approach to channel routing," 1991 International Symposium on Circuits and Systems, Singapore, June 11, 1991. (EI)

76. S. C. Fang, K. E. Chang, W. S. Feng, and S. J. Chen, " Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems," 28th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, pp. 60-65, June 17, 1991. (EI)

77. C. J. Chen, J. M. Shyu, and W. S. Feng, "Transient sensitivity computation for waveform relaxation-based timing simulation," ICCAD-91: International Conference on Computer-aided Design, Santa Clara, CA, USA, November 10-14, pp. 120-123, 1991. (EI)

78. J. H. Wang, M. Chang, and W. S. Feng, "Considerations of internal charges on computing delay," Proceeding of Third VLSI/CAD Workshop, pp. 205-213, 1992.

79. J. H. Wang, J. T. Fan, and W. S. Feng, "A novel current model for CMOS gates," The 1992 IEEE International Symposium on Circuits and Systems, San Diego, pp. 2132-2135, 1992. (EI)

80. S. C. Fang, W. S. Feng, and S. L. Lee, "A new efficient approach to multilayer channel routing problem," 29th ACM/IEEE Design Automation Conference, Anahan, CA, USA, pp. 579-584,June, 1992. (EI)

81. J. H. Wang, J. T. Fan and W. S. Feng, "A recursive algorithm for computing delays in RC networks with internal charges," The 1992 IEEE International Symposium on Circuits and Systems, San Diego, pp. 2132-2135, May 10-13, 1992. (EI)

82. J. H. Wang, M. Chang and W. S. Feng, "The effects of internal charges to waveform calculation," ASIA-PACIFIC Conference on Circuits and Systems,Australia, 8-11, Dec., 1992, pp.271-276. (EI)

83. H. C. Chow and W. S. Feng, "A short-channel CMOS inverter propagation delay model suitable for timing verification," ASIA-PACIFIC Conference on Circuits and Systems, Australia, 8-11, Dec., 1992, pp. 448-453. (EI)

84. J. H. Wang, M. Chang and W. S. Feng, "Delay calculation by using novel logical expression," ASIA-PACIFIC Conference on Circuits and Systems, Australia, 8-11, Dec., 1992, pp.454-459. (EI)

85. J. H. Wang, J. T. Fan and W. S. Feng, "Accurate current model for CMOS gates," JTC-CSCC'93: 1993 Joint Technical Conference on Circuit/Systems, Computers and Communications, NaraJapan, July 26-28, 1993, pp.546-550.

86. J. T. Fan, J. H. Wang, and W. S. Feng, "WBCS - An accurate and tableless current simulator for CMOS gates," Fourth VLSI Design/CAD Workshop,NantouTaiwan, R.O.C., Proceedings 1993, pp.66-71.

87. W. S. Feng, W. T. Yang, and M. Y. Hsieh, "Computer-aided design on the VLSI 45-degree mask compaction," TENCON'93/BeijingChina, Oct. 19-21, 1993, pp.750-753. (EI)

88. J. H. Wang, M. L. Chang and W. S. Feng, "An accurate time-domain current waveform simulator for VLSI circuits," EDAC: The European Design Automation Conference, ParisFrance, Feb. 28, 1994, pp. 562-566. (EI)

89. C. J. Chen and W. S. Feng, "Transient sensitivity computation of MOSFEET circuits using iterated timing analysis and selective-tracing waveform relaxation," 31th ACM/IEEE Design Automation Conference, San Diego, CA, USA, pp 581-585, June, 1994. (EI)

90. W. S. Feng, Jims J.H. Wang, M. Chang and W. C. Yang, "Waveform-based Timing Simulator for MOS Circuits, " 1995 National Electron Devices and Materials Symposium, KauhsiungTaiwan, R.O.C. July 6, 1995.

91. W. S. Feng, W. T. Chien, and W. C. Yang, "Signal probability for CMOS power-delay evaluation," 1995 National Electron Devices and Materials Symposium, KauhsiungTaiwan, R.O.C. July 6, 1995.

92. W. S. Feng, W. T. Chien, and W. C. Yang, "CMOS power-delay product verification using signal probability," The 6th VLSI/CAD symposium, Chaiyi, Taiwan, R.O.C., August 17-19, 1995, pp.107-110.

93. W. S. Feng, "A fast multilayer router for crosstalk reduction on MCM/PCB (Invited Speaker & Chairman)," Proc. of High-Speed Board Design Seminar, Asian Electronics Engineers, TaipeiTaiwan, ROC, Dec.6, 1995, pp.1-25.

94. W. S .Feng and C. K. Yang, "Distributed timing simulator for MOSFET circuits," 1996 Semiconductor Technology CAD workshop and Exhibition, Hsinchu,Taiwan, R.O.C., May 15, 1996.

95. B. Y. Ma, T. H. Liu and W. S. Feng, "Modeling and torque pulsation reduction for a switched reluctance motor drive system," Proc. of the 1996 IEEE IECON, TaipeiTaiwan, R.O.C., pp.72-77, August 5-10 1996. (EI)

96. W. S. Feng and C. K. Yang, "Distributed circuit simulator for MOSFET timing analysis," The 7th VLSI/CAD symposium, TaoyuanTaiwan, R.O.C., pp.101-104, August 15-17, 1996.

97. M. L. Chang, S. J. Yih and W. S. Feng, "Estimation of delay due to overshoot effect for CMOS gates in binary-tree timing simulation,"International Conference on Computer, KaohsiungTaiwan, ROC, pp.229-235, Dec. 12-14, 1996.

98. W. J. Ho, M. S. Lio and W. S. Feng, "A new single-phase on-line UPS structure pre-staged with PFC-and-boost Converter," PEDS'97: Second International Conf. on Power Electronics & Drive Systems, Singapore, pp.133-138, May 26-29, May 1997. (EI)

99. W. J. Ho, M. S. Lio and W. S. Feng, "Common-neutral type AC/DC/AC topologies with PFC regulator," PEDS'97: Second International Conf. on Power Electronics & Drive Systems, Singapore, pp. 53-58, May 26-29, 1997. (EI)

100. W. J. Ho, J. B. Lio and W. S. Feng, "A line-interactive UPS structure with built-in vector-controlled charger and PFC,PEDS'97: Second International Conf. on Power Electronics & Drive Systems, Singapore, pp.127-132, May 26-29, 1997. (EI)

101. B. Y. Ma, T. H. Liu, C. G. Chen, T. J. Shen and W. S. Feng, "Design and Implementation of a sensorless switched reluctance drive system,"PEDS'97: Second International Conf. on Power Electronics & Drive Systems, Singapore, pp.174-180, May 26-29, 1997. (EI)

102. W. S. Feng and Y. H. Tseng, "EMC-driven placement for MCM," EMC'97, International Symposium on Electromagnetic Compatibility, BeijingChina, pp.364-367, May 21-23, 1997. (EI)

103. S. J. Yih, M. L. Chang and W. S. Feng, "Improvement in radiation-hard CMOS logic gates for noise margin," 1997 IEEE International Symposium on Circuits and Systems, Hong Kong, pp.1916-1918, Jun. 1997. (EI)

104. M. L. Chang, S. J. Yih and W. S. Feng, "Recursive algorithms based on MTB tree for estimating delays in RC tree circuits with considering charge sharing effect," 1997 IEEE International Symposium on Circuits and Systems, Hong Kong, Jun. 1997, pp.1696-1699. (EI)

105. W. S. Feng and W. M. Wei, "Estimation of power dissipation with pattern search," The 8th VLSI Design/CAD Symposium, Nantou, pp. 109-112, Aug. 1997.

106. M. L. Chang, S. J. Yih, and W. S. Feng, "The estimation of bottle neck effect in waveform-based switch-level timing simulaiton," The 8th VLSI Design/CAD Symposium, Nantou, pp.233-236, Aug. 1997.

107. W. S. Feng, "Board-level layout technologies for next decades," 1997 ICHT: International Conference on High Technology, ChangHua, pp. 58-65, Aug. 1997.

108. W. S. Feng, S. Denqchen and M. C. Chen, "Simulation and optimization of MCM interconnections," IMAPS-International Microelectronics and Packaging Society, Denver, CO, pp.178-183, April 14, 1998. (EI)

109. M. L. Chang, W. J. Chen, J. H. Wang and W. S. Feng, ”Waveform approximation technique in the switch-level timing simulator BTS,”ISCAS'98: International Symposium on Circuits and Systems, MontereyCA, May 1998. (EI)

110. Z. C. Lin, S. Tenqchen, W. S. Feng and M. C. Chen, ”An electromagnetic simulation for the interconnections of multilayered packaging: MCM/PCB,” The 9th VLSI/CAD Symposium, NantouTaiwan, ROC, pp.45-48, Aug. 1998.

111. J. H. Wang and W. S. Feng, ”Glitch processing in current waveform simulation of CMOS integrated circuits,” The 9th VLSI/CAD Symposium,NantouTaiwan, ROC, pp.61-64, Aug. 1998.

112. T. H. Liu, B. Y. Ma, C. J. Chen and W. S. Feng, “Implementation of a high performance permanent magnet synchronous drive with reduced switching frequency and loss,” IEEE International Conference on Industrial Electronics, Control, and Instrumentation, 1998. (EI)

113.馬斌嚴,劉添華,沈,馮武雄, “無轉軸位置偵測元件切換式磁阻驅動系統的研製,” 中華民國第十七屆電力工程研討會, 第76-80 , 1997.

114.馬斌嚴,劉添華,陳國慶,馮武雄, “新型無轉軸偵測元件開關式磁阻驅動系統的研究,”中華民國第十八屆電力工程研討會, 第16-20 , 1998.

115.陳志榮,劉添華,馬斌嚴,馮武雄, “改良式無刷驅動系統的研究,” 中華民國第十八屆電力工程研討會, 第11-15 , 1998.

116. L. D. Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A tree-systolic array of DLMS adaptive filter," ICASSP: 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing, Mar. 1999, Vol.3, pp.1253-1256, Phoenix, Arizona. (EI)

117. W. S. Feng, M. C. Suen, Z. C. Lin, and V. Lu, "Efficient simulation and optimization for multilayered interconnections," DATE'99: Design, Automation and Test, Mar. 1999, pp.128-131, MunichGermany. (EI)

118. L. D. Van, S. S. Wang, S. Tenqchen, W. S. Feng, and B. S. Jeng, "Design of a lower-error fixed-width multiplier for speech processing application," in Proc. IEEE Int. Symp. Circuits Syst., May 1999, Vol.3, pp.130-133, OrlandoFlorida. (EI)

119. F. C. Lin, N. S. Wang, and W. S. Feng, “Design and implementation of Gaussian MSK receiver for wireless communication system,” Proc. of the Tenth VLSI Design/.CAD Symposium, August 18-24 1999, pp.251-254, , Nantou,Taiwan.

120. W. S. Feng, H. J. Lee, and M. C. Chen, “Optimization technique for multilayered interconnections,” EDMS’99, Nov. 1999, pp.145-148, Taoyuan,Taiwan.

121. L. D. Van, C. C. Tang, S. Tenqchen, and W. S. Feng, "A new VLSI architecture without global broadcast for 2-D digital filters,in Proc. IEEE Int. Symp Circuits Syst., May 2000, Vol.1, pp.547-550, Geneva, Switzerland. (EI)

122. W. S. Feng, “2.4-GHz CMOS Mixer Design,” 2000 Strait Radio Science Conference, Sept. 2000, pp. 133-136, Hefei, China.

123. L. D. Van, M. C. Sun, S. Tenqchen, C. H. Chang and W. S. Feng, “A new 2-D digital filter using a locally broadcast scheme and its cascade form,” in Proc. IEEE Asia Pacific Conf. on Circuits Syst., Dec. 2000, Tianjin, China, pp. 579-582. (EI)

124. L. D. Van and W. S. Feng, “Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters,” in Proc. IEEE Asia Pacific Conf. on Circuits Syst., Dec. 2000, Tianjin, China, pp.399-402. (EI)

125. S. Tenqchen, M. C. Sun, W. S. Feng, “Design of a Normalized Delayless LMS Adaptive Subband Digital Filter,” Control Application, 2000, Proceedings of the IEEE International Conference on, pp. 513-518. (EI)

126.馮武雄, “RF CAD 電路測試與驗證研究” 2000 年全國電信研討會暨國科會電信學門研究成果發表,桃園中壢市,pp.270-273.

127.馮武雄, “RF 元件模式設計與參數擷取研究” 2000 年全國電信研討會暨國科會電信學門研究成果發表,桃園中壢市,pp.274-276

128. W. S. Feng, Y. S. Shou and S. Tenqchen, “A double-sampled fourth-order bandpass sigma-delta modulator with reduced number of Op Amps,” in Proc. of the 11th VLSI Design/CAD Symposium, August 16-19 2000, pp.289-292, Pintung, Taiwan.

129. C. C. Tan, W. S. Lu, L. D. Van and W. S. Feng, “A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage,” IEEE International Symposium on Circuits and Systems, pp. IV-794-797, 2001. (EI)

130.W. S. Feng, “Implementation of CMOS RF Power Amplifier,” Cross Strait Tri-Regional Radio Science and Wireless Technology Conference, PeikingChina, 2001.

131.馮武雄,賴銘宏,許振賢,簡燦男, “RF 元件模式設計與CMOS 混頻器設計” 第一屆台塑集團應用工程技術研討會, 桃園龜山, July 2001, pp. B0004.

132.李恆哲,朱家齊,馮武雄, “超大型積體電路之時鐘樹合成軟體設計” 第一屆台塑集團應用工程技術研討會, 桃園龜山, July 2001, pp. B0008.

133..夏勤,賴銘宏,朱家齊,馮武雄, “剪化無格點式之積體電路繞線工具程式設計與開發”第一屆台塑集團應用工程技術研討會, 桃園龜山, July 2001, pp. B0009.

134..馮武雄, 唐志淳, ‘CMOS 5.8GHz 前端放大電路’, 第八屆海峽兩岸無線電技術研討會, 四川 成都, Sept 2001, pp.285-288.

135.W. S. Feng, “功率元件之高頻特性研究,” in Proc. of the 11th VLSI Design/.CAD Symposium, Aug 2001, HsinchuTaiwan.

136.W. S. Feng, and C. C. Tang, “CMOS 2.4GHz 射頻低雜訊放大器,” CIC 2000 IC Design Fruitful Announce Meeting, HsinchuTaiwan, Aug. 2001.

137. W. S. Feng, “An Auto-Router for Multichip Modules,” CIC 2000 IC Design Fruitful Announce Meeting, HsinchuTaiwan, Aug. 2001.

138.W. S. Feng, “Design and Implementation of CMOS RF Power Amplifier,”CIC 2000 IC Design Fruitful Announce Meeting, HsinchuTaiwan, Aug. 2001.

139.W. S. Feng, “2.4-GHz active-load low-noise amplifier,” Cross Strait Tri-Regional Radio Science and Wireless Technology Conference, ShanghaiChina, pp.199-201, 2002.

140.S. Tenqchen, M. C. Sun and W. S. Feng, “Robust Synthesis in l1 via Approach and D-K iteration,” The 2002 45th Midwest Symposium on Circuits and Systems, TulsaUSA, Aug. 2002, vol.3, pp.III-105-108.( EI)

141.S. Tenqchen, Y. –H. Shu,W. S. Feng, and B. S. Jeng, “Design of an Efficient RAKE Receiver Architecture for Multiuser Detection with Adaptive Channel Estimation,” IECON'02 - 28 Annual Conference of the IEEE Industrial Electronics Society, Sevilla, Spain, Nov 5 to 8, 2002, pp.2357-2364. (EI)

142.S. Tenqchen, J. H. Chang, Wu-Shiung Feng and Bor-Sheng Jeng, “Pipelining Extended Givens Rotation RLS Adaptive Filters,” IEEE DELTA2002, at Christchurch, New Zealand, pp.466~473. Jan. 29-31,2002. (EI)

143.S. Tenqchen, Y.-H. Shu, Ming-Chang Sun and Wu-Shiung Feng, “Robust Synthesis in l1 via Approach,” 6th World Multiconference Systemics, Cybernetics and Information, IEEE SCI2002, at FloridaUSA, 2002.) (EI)

144.S. Tenqchen, M.-C. Sun, Wu-Shiung Feng and B. S. Jeng, “Block decision feedback multiuser detector for intersymbol interference channels for CDMA system,” 2002 IEEE International Symposium on Intelligent Signal processing and Communication Systems, Ambassador Hotel, Kaohsiung, Taiwan, R. O. C., 2002, pp.442-447. (EI)

145.S. Tenqchen, M.-C. Sun, Wu-Shiung Feng and B. S. Jeng, “Design of Nonlinear Equalizer with Decision-Feedback Filter for RAKE Receiver,”The 2002 IEEE International Midwest Symposium on Circuits and Systems, Tulsa,OklahomaUSA, 2002. (EI)

146.Chin Hsia, Ming-Hung Lai, Wu-shiung Feng, “On-board effective inductance measurement,” APCCAS’02: 2002 Asia-Pacific Conference on Circuits and Systems, Vol. 1, Bali, Indonesia, Oct. 2002, pp.443-446. (EI)

147.H.-J. Lee; C.-C. Chu; W. S. Feng, “Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models  APCCAS '02: 2002 Asia-Pacific Conference on Circuits and Systems, Vol. 1, 2002, pp. 257 –262. (EI)

148.H.-J. Lee; C.-C. Chu; W. S. Feng, “Intelligent multipoint arnoldi (IMA) approximations of FIR filters by low-order linear-phase HR filters,” ISCAS 2002: IEEE International Symposium on Circuits and Systems, Vol. 1, 2002, pp. 417 –420. (EI)

149.S. Tenqchen, M.-C. Sun, W.-S. Feng,and B. S. Jeng, Robust Synthesis in l1via Approach and D-K iteration,” 45th IEEE Midwest Symposium on Circuits and Systems, TulsaOklahomaUSA, pp.III-105~108, 2002. (EI)

150.W. S. Feng, “The study on the high-performance partitioning techniques for million-gate”, 國科會微電子學門專題計劃研究成果發表會, 曾文水庫, 台南,2002.

151.賴銘宏,夏勤,簡燦男,馮武雄, “電路板設計中電感量測電路設計,” 第四屆台灣電磁相容研討會, 台北, pp. 111-124, Oct. 2002.

152.H.-J. Lee; C.-C. Chu; W. S. Feng, “Crosstalk noise analysis of coupled RLC trees using moment matching techniques,” Proc. of the 2002 VLSI Design/CAD symposium, Taiwan, 2002, pp.388-391.

153.Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng and Bor-Sheng Jeng, “Design of CORDIC-Based 16-QAM for Multiuser Detection in W-CDMA system,”ICS: International Computer Symposium, Kaohsiung, Taiwan, R. O. C., 2002.

154.H. J. Lee, C. C. Chu and W. S. Feng, “Crosstalk estimation of coupled RLC trees in high-speed VLSI interconnects using stable-pole models”, in Proc. the 13th VLSI Desing/CAD Symposium, Taitung, Taiwan, 2002.

155. H. J. Lee, C. C. Chu and W. S. Feng, “Interconnect modeling and sensitivity analysis using adjoint networks reduction technique,” in Proc. the 2003 International Symposium on Circuits and Systems, pp. 648-651, Bangkok, Thailand, May 25-28 2003. (EI)

156. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng, “Harmonic Retrieval Using Cumulant-Based Estimator for ARMA Systems,” ICICS-PCM 2003 - the Fourth International Conference on Information, Communications & Signal Processing and Fourth Pacific-Rim Conference on Multimedia, Singapore, Vol. 2, Dec. 15-18 2003. pp. 1235–1238. ( EI)

157. M.-C. Sun, S. Tenqchen, Y.-H. Shu, W.-S. Feng, “A 2.4 GHz CMOS Image-Reject Low Noise Amplifier,” IEEE 2003 International Symposium on Circuits and Systems, BangkokThailand, pp.I-329-332, May 25-28, 2003. (EI)

158. Meng-chou Chang, Zong-xin Lin, Rong-yau Tsai, Hsiao-lung Chan, and Wu-shiung Feng, “Design of an ARM-based System-on-Chip for Real-time QRS Detection in Electrocardiograms,” 2003 International Conference on Informatics, Cybernetics, and Systems, KaohsiungTaiwan, ROC, Dec. 14-16, 2003, pp.319-324. (EI)

159. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng “Calculation the Infinite norm ball of Constant Modulus Receivers for QAM System by D-K iterations” 2003 IEEE Workshop on Signal Processing Systems (SiPS’03), Souel,Korea, pp.126-132, Aug. 27-29 2003. (EI)

160.H. J. Lee, C. C. Chu and W. S. Feng, “Moment computations of distributed coupled RLC trees with applications to estimating crosstalk noise,” in Proc. the 14th VLSI Desing/CAD Symposium, Hualien, Taiwan, 2003, pp. 285-288.

161.H. J. Lee, C. C. Chu and W. S. Feng, “Crosstalk Noise Estimations for Nonuniform Distributed Coupled RLC Lines Using Model-Order Reduction Techniques”, 2003 Taiwan EMC Conference, Taipei, Taiwan, 2003, pp.200-205.

162.邱安平、施權峰*、王宥楠、曾建元、陳乃權、張本秀、馮武雄, ”新式TLM 模型及其在氮化鎵歐姆接觸特性量測之應用,” 2003 Electronic Devices and Materials Symposium, Keelung, Taiwan, Rep. of China, pp.380-383, Nov. 2003.

163.施權峰、陳乃權、邱安平、王宥楠、鄧順達、王明程、馮武雄, “Effect of surface work function of p-type GaN on the electrical properties of blue LED”

164. 王宥楠、施權峰*、邱安平、陳乃權、張本秀、王明程、吳國梅, “氮化合物發光二極體工作電壓簡易分析法,”

165. C. F. Shih、N. C. Chen、A. P. Chiu、L.. N. Wang、S. D. Tenq、M. C. Wang、W. S. Feng, “Effect of surface work function of p-type GaN on the electrical properties of blue LED” 2003 Electronic Devices and Materials Symposium, Keelung, Taiwan, Rep. of China, pp.862-864, Nov. 2003.

166. L. N. Wang、C. F. Shih *、A. P. Chiu、N. C. Chen、P. S. Chang、M. C. Wang、G. M. Wu, “A simple measurement for the operating voltage of GaN LEDs,” 2003 Electronic Devices and Materials Symposium, KeelungTaiwan, Rep. ofChina, pp.924-927, Nov. 2003.

167. 馮武雄, “氮化合物半導體專題-從磊晶到光電元件 (invited paper)” 2003 Electronic

Devices and Materials Symposium, KeelungTaiwan, Rep. of China, pp.924-927, Nov. 2003.

168. C. W. Lin, Y. H. Liu, W. S. Feng, and W. C. Lai, “A Fully Integrated 2.4GHz Differential Low Noise Amplifier,” 第三屆台塑集團應用工程技術研討會, 桃園龜山, Dec. 19, 2003, p. D07.

169. C. W. Lin, W. C. Lai and W. S. Feng, “Development of 5.7 GHz RF transceiver front-end chipset in 0.25 μm CMOS,” 第三屆台塑集團應用工程技術研討會, 桃園龜山, Dec. 19, 2003, p. D08.

170. C. W. Lin, Y. H. Liu, W. S. Feng, and W. C. Lai, “A Fully Integrated 5.8GHz CurrentReuse Low Noise Amplifier,” 第三屆台塑集團應用工程技術研討會, 桃園龜山, Dec. 19, 2003, p. D09.

171. C. W. Lin, Y. H. Liu, W. S. Feng, and W. C. Lai, “A Fully Integrated High Linearity Variable gain Dual-Band CMOS LNA,” 第三屆台塑集團應用工程技術研討會, 桃園龜山, Dec. 19, 2003, p. D10.

172. 王宥楠、陳乃權、施權峰*、邱安平、曾建元、張本秀、王明程、吳國梅、馮武雄、劉國雄, “NTLM(New Transmission Line modeling)理論對氮化鎵歐姆接觸特性之量測分析” 第三屆台塑集團應用工程技術研討會, 桃園龜山, Dec. 19, 2003, p. C-07.

173. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng, “Harmonic Retrieval Using Cumulant-Based Estimator for ARMA Systems,” Fourth International Conference on Information, Communications & Signal Processing Fourth IEEE Pacific-Rim Conference On Multimedia, 15-18 December 2003, Singapore, ( EI)

174. W. S. Feng, “Experience and Corporation with HwaYa Science Park”, 92 年國科會微電子學門成果發表會, 台北, Nov. 29-30, 2003.

175. W. S. Feng, “生理檢測訊號系統的SoC 晶片設計,” SoC 趨勢高峰論壇,Taoyuan,Taiwan, Dec. 2003.

176 馮武雄, “科技創業-以產業研究型大學為例,” 工程教育研討會,台北萬里,Jan. 18, 2003.

177. H. J. Lee, C. C. Chu, and W. S. Feng, “Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noise,” in Proc. The 5th International Symposium on Quality Electronic Design (ISQED2004), pp. 75-80, San Jose, CA, USA, 2004. ( EI)

178. H. J. Lee, C. C. Chu and W. S. Feng, “Generalizations of adjoint networks techniques for RLC interconnects model-order reductions,” in Proc. The 2004 International Symposium on Circuits and Systems, pp. I185-I188,VancouverBritish ColumbiaCanada, 2004. ( EI)

179. H. J. Lee, M. H. Lai, C. C. Chu and W. S. Feng, “Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops,” in Proc. The 2004 International Symposium on Circuits and Systems, pp. I713-I716, VancouverBritish ColumbiaCanada, 2004. ( EI)

180. H. J. Lee, C. C. Chu, and W. S. Feng, “Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders (RAMAO),” The 2004 IEEE Asia-Pacific Conference on Circuit and Systems, Dec. 6-9, 2004, Tainan, Taiwan, pp. 1009-1012. ( EI)

181. C. C. Chu, H. J. Lee, and W. S. Feng, “Error estimations of projection-based interconnect model-order reduction techniques,” The 2004 IEEE Asia-Pacific Conference on Circuit and Systems, Dec. 6-9, 2004, TainanTaiwan, pp.1085-1088. ( EI)

182. H. J. Lee, Ming-Hong Lai, C. C. Chu, and W. S. Feng, “Moment computations for R(L)C interconnects with multiple resistor loops using ROBDD techniques,” The 2004 IEEE Asia-Pacific Conference on Circuit and Systems, Dec. 6-9, 2004, Tainan, Taiwan, pp. 525-528. ( EI)

183. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng, “Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System,” IEEE DELTA2004, at PerthWestern Australia, Jan. 28-30, 2004, pp. 440-442. ( EI)

184. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng, “Beam Space-Time Coding for High-Speed Ultra-Wideband OFDM-based Wireless SystemInternational Conference on Computing, Communications and Control Technologies: CCCT'04, IIIS August 14-17, 2004, vol. 3, AustinTexasUSA, pp.250-256. (EI)

185. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng, “Space-Time Coding for Ultra-Wideband OFDM-based Wireless System,” in Proc. IEEE 47th MWCAS, HiroshimaJapan, vol. III, pp.235-238, 2004. (EI).

186. Meng-chou Chang, Zong-xin Lin, Che-wei Chang, Hsiao-lung Chan, and Wu-shiung Feng, 2004, December, “Design of a System-on-Chip for ECG Signal Processing,” The 2004 IEEE Asia-Pacific Conference on Circuit and Systems, Tainan, Taiwan, Dec. 6-9, 2004, pp.441-444. ( EI)

187. Meng-chou Chang, Zong-xin Lin, Rong-yau Tsai, Hsiao-lung Chan, and Wu-shiung Feng, 2003, December, “Design of an ARM-based System-on-Chip for Real-time QRS Detection in Electrocardiograms,” 2004 International Conference on Informatics, Cybernetics, and Systems, KaohsiungTaiwan, pp.319-324. (EI)

188. Ying-Haw Shu, S. Tenqchen, M.-C. Sun, and W.-S. Feng, “A XNOR based Double Edge-Triggered Flip-Flop Used in Two-Phase Pipelines,”International Conference on Computing, Communications and Control Technologies: CCCT'04, IIIS August 14-17, 2004, vol. I, pp.79-84, AustinTexas, USA.(EI)

189. J. R. Tsai, L.W. Ho, S.H. Lin, T.C. Chang*, M.D. Shieh*, H.C. Lin**, C.P. Lin, W.S. Feng, and R.D. Chang, “Transient Behavior of Phosphorus Dose Loss and Modeling of Dopant Segregation at the Si/SiO2 Interface,” 2004 IEDM: IEEE International Electron Devices Meeting, San Francisco, CA, USA, Dec. 15, 2004, pp.39.5.1-39.5.4. (EI)

190. H. J. Lee, C. C. Chu, and W. S. Feng, “An adaptive-order rational Arnoldi method for model-order reductions of linear time-invariant systems,” accepted for publication in the 10th IFAC/IFORS/IMACS/IFIP Symposium on Large Scale Systems: Theory and Applications, OsakaJapan, July 26, 2004. (LSS2004).

191. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng “Blind Separation of Convolutive Mixture Algorithm for the License Plate Matching”, in Proc. IEEE ICIP’04, Singapore.(EI)

192. S. Tenqchen, Y.-H. Shu, M.-C. Sun, and W.-S. Feng “Beam Space-Time of a BER Minimized OFDM Systems With Bezout Precoders” The 6th WSEAS TELE- INFO’ 04, CancunMexico, May 12-15, 2004. (EI)

193. Ying-Haw Shu, S. Tenqchen, M.-C. Sun, and W.-S. Feng “Two Efficient Pipelined Designs for MIMO Asynchronous Control,” The WSEAS 6th TELE- INFO’ 04, CancunMexico, May 12-15, 2004. (EI)

194. W. S. Feng, “Embedded Bio-medical Diagnosis System-on-Chip Design,” ROC-Belgium Nano-SOCConference, LeuvenBelgium, Sept. 24, 2004.

195.W. S. Feng and C. -C. Hung, “A Low Voltage, Variable Gain Design for Low Noise Amplifier,” in Proc. the 15th VLSI Desing/CAD Symposium, Pintong, Taiwan, Aug. 10-13, 2004, p. P2-7, p.43.

196.Bo-Wei Chen, Hsiao-Chen Chen, Hwang-Cherng Chow and Wu-Shiung Feng, “A 1.8V, 0.3mW, 10-Bit SA-ADC with New Self-Timed Timing Control for Biomedical Applications,” in Proc. the 15th VLSI Desing/CAD Symposium, Pintong, Taiwan, Aug10-13, 2004, p. P2-23, p.51.

197.H. J. Lee, M. H. Lai, C. C. Chu and W. S. Feng, “Tree/link Partitioning for Moment Computations of General Lump R(L)C Interconnect Networks with Multiple Resistor Links,” in Proc. the 15th VLSI Desing/CAD Symposium, Pintong, Taiwan, Aug. 10-13, 2004, A4-3, p.79.

198.W. S. Feng, “重點科技留學及菁英回國卓越發展環境,”2004 大專校院工程及技術學院校院長會議, 中國工程教育學會,台東, Jan. 9-10, 2004.

199.H. J. Lee, C. C. Chu and W. S. Feng, “Moment computations of distributed coupled RLC trees with applications to estimating crosstalk noise,” in Proc. the 15th VLSI Desing/CAD Symposium, PintongTaiwan, Aug. 10-13, 2004.

200. W. S. Feng, “Design of a 2.4GHz variable-gain low-noise amplifier,”Cross Strait Tri-Regional Radio Science and Wireless Technology Conference (CSTRW2005) , BeijingChina, pp.161-164, 2005

201. W. C. Lai and W. S. Feng, “5.7GHz CMOS High Linearity RF Power Amplifier (高線性功放大器之應用),” Cross Strait Tri-Regional Radio Science and Wireless Technology Conference (CSTRW2005), BeijingChina, pp.172-175, 2005.

202. Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen and Wu-Shiung Feng ,”A 1.8V, 0.3mW, 10-Bit SA-ADC with new self-timed timing control for biomedical applications,” 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, pp. 736-739. (EI)

203. C. C. Chu, H. J. Lee, W. S. Feng, and M. H. Lai, “Interconnect model reductions by using the AORA algorithm with considering the adjoint network,” 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, 1278-1281. (EI)

204. Shing TenqChen, Chi-Chu Ku, Wu-Shiung Feng , and Chao-Hao Lee, “Hopping Pilot Performance Analysis of PPM-TH and PAM-DS UWB Radio Link Based on Coherent Correlation Detection,” the Fifth International Conference on Information, Communications and Signal Processing (ICICS), Bangkok, Thailand, Dec. 6, 2005, pp.286-290.

205. Chien-Cheng Wei, Hsien-Chin Chiu, and Wu-Shiung Feng, “An Ultra-Wideband CMOS VCO with 3~5GHz Tuning Range,” IEEE International Workshop on Radio-Frequency Integration Technology, Singapore, Nov. 30 – Dec. 2, 2005, pp.87-90.

206. G. M. Wu, C. W. Tsai, C. F. Shih, N. C. Chen, W. H. Feng, 2005, “GaN/Si(111) epilayer based on low temperature AlN and AlGaN/GaN superlattice for light emitting diodes,” Solid State Phenom, in press (SCI)

207. W. S. Feng, W. C. Lai, and C. C. Wang, “Application of 5.7-GHz CMOS variable power Amplifier,” 第四屆台塑企業應用工程技術研討會, 台北泰山, May 27, 2005, G-2-006, p.201.

208. M. H. Lai, C. C. Chu, and W. S. Feng, “應用非對稱性Lanczos 法之高速VLSI 互連結構模型化簡技巧,” 第四屆台塑企業應用工程技術研討會, 台北泰山, May 27, 2005, G-4-036, p.229.

209. M. H. Lai, C. C. Chu, and W. S. Feng, “建構超大型類比積體電路巨觀模型化簡技巧, ”第四屆台塑企業應用工程技術研討會, 台北泰山, May 27, 2005, G-4-039, p.232.

210. Wu-Shiung Feng, Herng-Jer Lee, Chia-Chi Chu, and Ming-Hong Lai, “Method of Moment Computations in R(L)C Interconnects of High Speed SoC with Resistor Loops,” in Proc. the 16th VLSI Desing/CAD Symposium, Hua-Lien, Taiwan, Aug. 9-12, 2005, p.p2-23, p.51.

211. Herng-Jer Lee, Chia-Chi Chu, and Wu-Shiung Feng, “Efficient Moment Computations for Interconnect Coupled RLC-Tree Networks,” in Proc. the 16th VLSI Desing/CAD Symposium, Hua-Lien, Taiwan, Aug. 9-12, 2005, p. P3-20, p.62.

212. C. Chu, M. H. Lai, and W. S. Feng, “The Global Lanczos Method for MIMO Interconnect Order Reductions,” 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24 2006, pp.1103-1106. (EI)

213. C. C. Chu, M. H. Lai, and W. S. Feng, “The Global Lanczos Method for MIMO Interconnect Order Reductions,” 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006, pp.1103-1106. (EI)

214. M. H. Lai, C. C. Chu, and W. S. Feng, “MIMO Interconnects Order Reductions by Using the Global Arnoldi Algorithm,” 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, pp.1107-1110. (EI)

215. Chien-Cheng Wei, Hsien-Chin Chiu, and Wu-Shiung Feng, “High Linearity Performance of 0.1μm CMOS Devices using Field-Plate Technology,” 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, San Francisco, June 11, 2006, pp.525-528.(EI)

216. C. C. Wei, H. -C. Chiu and W. -S. Feng, “A Low Noise 3.1-10.6 GHz CMOS Distributed Amplifier for Ultra-Wideband Applications,” 2006 CSTRW ,MacauChina, Aug. 2006, pp.209-212.

217. W. S. Feng and C. M. Liu, “Bow-tie Antenna Design for UWB Applications,” 2005 CSTRW, MacauChina, Aug. 2006, pp.423-426.

218. M. H. Lai, C. C. Chu, and W. S. Feng, “The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions,” APCCAS2006 IEEE Asic-Pacific Conference on Circuits and Systems, Singapore, Dec.4, 2006, pp. 1270-1273. (EI)

219. M. H. Lai, C. C. Chu, and W. S. Feng, “Model-Order Reduction Algorithm with Structure Preserving Techniques,” APCCAS2006 IEEE Asic-Pacific Conference on Circuits and Systems, Singapore, Dec.4, 2006, pp. 1609-1612 . (EI)

220. 卓政憲,馮武雄 “Organic Materials and Low-temperature IZO film for TFT Display,” 第五屆台塑關係企業應用技術研討會,June 2006, pp. N02-1-4.

221.林昌摑、童信龍、馮武雄 “應用於超寬頻帶3.1~10.6 GHz射頻前端接收電路,” 第五屆台塑關係企業應用技術研討會,June 2006, pp. O01-1-4.

222.傅泰順、馮武雄 “應用於超寬頻系統之低雜訊放大器,” 第五屆台塑關係企業應用技術研討會,June 2006, pp. O02-1-4.

223.C. H. Cho and W. S. Feng, “Application of Organic Materials and Low-Temperature IZO film for TFT Display-Matrix Technology,” The TaiwanDisplay Conference, Taipei, June 2006, p.07-001.

224.Wu-Shiung Feng, Chen-Yuan Chu, Chien-Cheng Wei and Ming-Chang Sun, “A 5.7 GHz Image-Reject CMOS Low-Noise Amplifier using A New Design Technique,” 17th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 8,2006, pp. C3-4. NSC94-2218-E-182-006

225. Ming-Hong Lai, Chia-Chi Chu and Wu-Shiung Feng, “The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reduction,”17th VLSI Design/CAD Symposium, HualienTaiwan, Aug. 8,2006, pp. D1-11. NSC93-2213-E-182-001

226. Ming-Hong Lai, Chia-Chi Chu and Wu-Shiung Feng, “Model-Order Reduction Algorithm with Structure Preserving Techniques,” 17th VLSI Design/CAD Symposium, HualienTaiwan, Aug. 8,2006, pp. D1-11. NSC93-2213-E-182-001

227. Chien-Cheng Wei, Hsien-Chin Chiu, and Wu-Shiung Feng, “An Improved BSIM4 Model for 0.13-μm Gate-length High Linearity CMOS RF Transistors,” Progress In Electromagnetics Research Symposium (PIERS07), Beijing, China, pp.1052-1056, Mar. 2007. (EI)

228. Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng, “Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis,” ISCAS, New Oreland, May 2007, pp.1133-1136. (EI)

229. Chien-Cheng Wei, Hsien-Chin Chiu, and Wu-Shiung Feng, “A 12-GHz Low Phase Noise VCO By Employing CMOS Field-Plate Transistors,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC07), Honolulu, Hawaii, pp.603-606, June 2007.(EI)

230. Chien-Cheng Wei, Shao-Wei Lin, Hsien-Chin Chiu, and Wu-Shiung Feng, “A Study of Gate/Source-terminated Field-Plate NMOS Transistors and Its application in Switch Design,” Asia-Pacific Microwave Conference (APMC07), Bangkok, Thailand, pp. 1091-1094, Dec. 2007. (EI)

231. Shing Tenqchen, Yung-Kuei Huang, Chao-Hao Lee, Wu-Shiung-Feng , and Charn-Kuo Wang, “Design of Middleware with EPC global by Using RFID Reader and Tag to Collect Traffic Information Implemented on Urban-bus,” ICSPCS'2007. (EI)

232. Chien-Cheng Wei, Hsien-Chin Chiu, Yi-Tzu Yang, and Wu-Shiung Feng, “A Novel Complementary Colpitts Differential CMOS VCO with Low Phase-Noise Performance,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC08), pp. 314-344, June 2008. (EI)

233. C. –Y. Chu, C. –C. Wei, S. –H. Feng and W, -S. Feng, “A 24GHz Low-Power CMOS Receiver Design,” 2008 ISCAS: International Symposium on Circuits and Systems, Seattle, USA, May, 2008, pp.980-983. (EI)

234. C. –C. Wei, H. –C. Hsu, H.- C. Chiu, and W. S. Feng,” A 24-GHz CMOS Sub-harmonic Mixer Located in Multilayer Marchand Baluns,” The 19th VLSI Design//CAD Symposium, Kenting, Taiwan, Sec.4-1, pp.1-4, Aug. 2008.

235. S. –C. Lai, C. –C. Wei, G. –C. Huang and W. –S. Feng,,” A 10GHz Low Phase Noise VCO Using Optimum Gate-Biasing and Transformer-Coupling Technology,” The 19th VLSI Design//CAD Symposium, KentingTaiwan, Sec. 9-6, pp.41-44, 2008.

236. L. –F. Chen, J. –R. Chen, C. –C. Wei and Wu-Shiung Feng, ” A Low-Power Impulse-Based UWB Transmitter,” The 19th VLSI Design//CAD Symposium, Kenting, Taiwan, Sec. 9-7, pp.45-48.

237. 陳立峰,陳俊叡,馮武雄, “低功率脈衝式超寬頻發射器” 2008 海峽兩岸三地無線電科技研討會,台北,pp.52-54, 97.8. (榮獲第三名)

238. 1. W. S. Feng, S. C. Lai, C. C. Wei, H. C. Chow and H. C. Hsu, “A Low Phase Noise 10-GHz VCO Using Dual-Transformer Coupling Technology,” Global Symposium of Millimeter Waves 2009 (GSMM2009), Sec. 2 ,Sendai, Japan, April 2009.

239. T. Y. Chang, S. M. Dai, H. J. Sheu, and W. S. Feng, “20-30GHz CMOS Transceiver Switch for UWB Applications,” CSTRWC2009, TianjinChina, Sec.B4, pp.1-4, Aug. 2009.

240. Chen-Hua Kuo and Wu-Shiung Feng,” The Optical Intensity and Attitude Detector for RFID” IEDM, Tao-YuanTaiwan, Nov. 19, 2009

241. Chia-Hsun Chen, Hui-Chen Hsu and Wu-Shiung Feng, “A 10-30 -GHz CMOS Distributed Amplifier for UWB Applications ” International Conference on Microwave and Millimeter Wave Technology(ICMMT), May 8, 2010. (Accepted)

242. Wu-Shiung Feng, Hui-Chen Hsu, Cheng-Ming Tsao, , Chia-Hsun Chen and Ho-Hsin Li, Chien-Cheng Wei, “Green Design Techniques for RF Front-end Circuits,” International Conference on Green Circuits and Systems (ICGCS 2010), Jun. 21, 2010. (Submitted)

Books:

1. 馮武雄編譯, "半導體元件物理學," 中央圖書出版社, 台北, 76 年 4 月.

2. 馮武雄、粱振坤編譯, "網路分析," 中央圖書出版社, 台北, 64 年 3 月.

Patents:

(國內核准專利)

1. 劉添華,馬斌嚴,陳國慶,馮武雄, “切換式磁阻馬達轉軸位置(角度)之估測方法,” 台灣大學, 發明第097017 號, 87.9.21-106.6.16.

2. 李恆哲,朱家齊,馮武雄,“快速決定時鐘樹上緩衝器種類並滿足時序設計規範之電路合成工具,” 長庚大學, 發明第197788 號, , 93.2.1-110.10.23.

3. 李恆哲,朱家齊,馮武雄,“以低階線性相位無限響應濾波器快速近似有限脈衝響應濾波器之數位濾波器設計工具,”長庚大學, 發明第I 222574 號, 2004.10.21-2022.5.22.

4. 李恆哲,朱家齊,馮武雄,賴銘宏“奈米積體電路估測分佈RLC 耦合互連線路串擾雜訊的設計方法與驗証,” 長庚大學, 發明第I 228227 號, 2005.2.21-2023.12.30.

5. 李恆哲,朱家齊,馮武雄”電路簡化模型求取方法與靈敏度分析法,” 長庚大學, 發明第I 233028 號, 2005.5.21-2023.6.16.

6. 馮武雄,李恆哲,朱家齊,賴銘宏, ”一種應用共軛網路運算進行高效率RLC 互連線路模型化簡之技巧,”長庚大學, 發明第I 252996 號, 2006.4.11-2024.10.17.

7. 李恆哲,何嘉銘、朱家齊,馮武雄”低耗能超大型積體電路可測性設計之掃描鍊重序方法," 發明第I 261767 號, 2006.9.11-2023.7.16. (Int. Cl.: G01R31/28(2006.01)

8. 馮武雄,李恆哲,朱家齊,賴銘宏, ”奈米積體電路中利用遞迴動差法估測非均勻性分佈式RLC 耦合互連線路串擾雜訊的驗証方法,” Patent No. I270796, 2007.1.11 (93.7.27)G06F17/50

9. 邱顯欽,魏建承,李緯憲,馮武雄, “高線性度及高功率CMOS 結構及其製造方法” 長庚大學, 發明第I270XXX 號, 2007.01.11 – 2024.10.07.

10. 李恆哲,朱家齊,馮武雄,賴銘宏“一種快速運算含電阻迴路之高速積體電路RLC 互連線路系統動差之技巧,”申請中華民國專利, 發明第I 276981 號,2007.03.21 –2024.06.07 , 申請日:2004.06.08( 申請號:093116448), NSC91-2218-E-182-001, G06F17/50。

11. 李恆哲,朱家齊,馮武雄,賴銘宏, ”高速超大型積體電路估測集總RLC 耦合互連線路串擾雜訊的方法” 發明第I 279697 號2007.04.21-2023.11.9, 2007.4.21 申請日:2003.11.10( 申請號:092131727) (Int. Cl.: G06F17/50(2006.01.12) ,NSC91-2218-E-182-001。

12. 馮武雄,朱家齊,李恆哲,張兆凱, "一種以Arnoldi 演算法誤差估測進行奈米積體電路互連線路模型化簡之方法," 發明第I287746 號2007.10.1 -

2026.06.16,:2005.6.17(094120265)(Int.Cl.:G06F9/455(2006.01), G06F17/50(2006.01)

13.賴銘宏,馮武雄,張兆凱,朱家齊, “一種同步考慮低時鐘歪曲率及低耗能之時鐘樹合成方法," 發明第I244015 號, 2007.01.11-2024.10.07 , 96.1.11 , 申請日:93.10.08(093130687)

14. 朱家齊,賴銘宏,馮武雄,卓昭儀 “搜尋積體電路設計中具有靜電放電威脅路徑之方法” 發明第I312119 號2007.10.1 - 2026.06.16, 申請日: 2005.6.17(094120265) (Int. Cl.:G05F17/17(2006.01), G06F17/16(2006.01),公告日:2009.07.11-2014/07/11,申請案號:095107254, 申請日:20063003,申請人:長庚大學

15. 朱家齊,賴銘宏,馮武雄, ”已全域Arnoldi 演算法發展超大型類比積體電路巨觀模的方法” 發明第I312122 號專利期間:2009/7/11-2026/3/2 申請日:2006/3/3( 申請號:095107250) (Int. G06F1750(2006.01), G06F17/16(2006.01) 。

(國外核准專利)

1. Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, and Ming-Hong Lai,    

“Method of verification of estimating crosstalk noise in coupled RLC   interconnects with distributed line in nanometer integrated circuits,” Chang Gung UniversityUnited States Patent, Patent No.: US 7,017,130 B2, (Date of Patent: Mar. 21, 2006).

2. Herng-Jer Lee, Chia-Ming Ho, Chia-Chi Chu, and Wu-Shiung Feng, “Method on Scan Chain Reordering for Lowering VLSI Power Consumption,” Chang Gung University, United States Patent, Patent No.: US 7,181,664 B2, (Date of Patent:2004/4/19 –2024/4/19) (Apply Number: 10/827,507) (Applied Date:2004/04/19 (Int. Cl.: G01R31/28)(2006.01) NSC91-2215-E-182 -001.

3. Herng-Jer Lee, Chia-Chi Chu, and Wu-Shiung Feng, “Method and Apparatus for Rapidly Selecting Types of Buffers which are Inserted into the Clock Tree for High-Speed Very-Large-Scale-Integration ,” Chang Gung University, United States Patent, Patent No.: US 7,191,418 B2, (Date of Patent:2004/7/12 – 2024/7/11) (Apply Number: 10/889,510)

(Applied Date: 2004/7/12 (Int. Cl.: G06F17/50)(2006.01) SC90-2215-E-182-001.

4.Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, and Ming-Hong Lai, “Method of Moment Computations in R(L)C Interconnects of High-Speed VLSI with Resistor Loops," Chang Gung University, Patent No.: US 7,254,790 B2, (Date of Patent: Aug. 7,2007), 2004/7/13-2024/7/122004/07/13, 10/889,795,G06F 17/50 (2006.01), G06F 17/10(2006.01)..

5. Ming-Hong Lai, Chao-Kai Chang, Chia-Chi Chu, and Wu-Shiung Feng, “Clock Tree Synthesis forLow Power Consumption and Low Clock Skew,” United States Patent, Patent No.: US 7,216,322 B2, CFP00428, 2004.09.07-2024.09.06, (Date of Patent: 2004.09.07) (Apply Number: 10/935,670) (International Classification: G06F17/50)(2006.01) NSC91-2218-E-182- 001.

6. Herng-Jer Lee, Chia-Chi Chu, and Wu-Shiung Feng, “Method and Apparatus for Model-Order Reduction and Sensitivity Analysis,” United States Patent, Patent No.:US 7,216,309 B2, CFP00382, 2004.0/5/6-2024/5/5, (Date of Patent: 2004/5/6) (Apply Number: 10/839,953) (Int. Cl.: G06F17/50 (2006.01),06F19/00(2006.01)G06F17/16, G06F17/16, G06F17/17, )(2006.01) NSC91-2218-E-182-001.

7. Herng-Jer Lee, Chia-Chi Chu, and Wu-Shiung Feng, “Efficient Digital Filter Design Tool for Approximating an FIR Filter with a Low-Order Linear-Phase IIR Filter,” United States Patent, Patent No.: US 7,373,367 B2, Period: 2004.0/04/19-2026/05/08, (Date of Application: 2004/04/19) (Apply Number: 10/827,504) (Int. Cl.: G06F17/10 (2006.01) NSC92-2218-E-182-001.

8. Mingt-Hong Lai, Chao-Yi Cho, Chia-Chi Chu, and Wu-Shiung Feng, “ Method of Searching Paths Suffering from the Electrostatic Discharge in the Process of an Integrated Circuit Design,” United States Patent, Patent No.: US 7,398,499 B2, Date of Patent: Jul. 8, 2008, Period: 2006/05/242026/06/03, (Date of Application:2006/05/24) (Apply Number: 11/440,349) (Int. Cl.: G06F17/50 (2006.01) (Patent Valid: 2008/07/08-2012/01/08) NSC92-2218-E-182-001.

9. Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng and ,Chao-Kai Chang, “Interconnect Model-Order Reduction Method,” US 7,437,689B2,2005/08/08-2026/0503,2005/08/08,11/199,026,G06F17/50(2006.1), 2008/10/14-2012/04/13.

10. Chia-Chi Chu, Ming-Hong Lai, and Wu-Shiung Feng, “Method of Determining High-Speed VLSI Reduced-Order Interconnect by Non-SymmetricLanczos Algorithm,"2009/03/24-2012/09/24: Patent No. US7,509,243B2, 2005/6/8-2025/6/7+267,2005/6/8, 11/148,086, G06F17/10(2006.01),G06F17/50(2006.01)

11. Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, and Chao-Kai Chang, “Multi-Point Model Reductions of VLSI Interconnects using the Rational Arnoldi Method with Adaptive Orders,"2009/03/31-2012/09/30: Patent No. US7,512,525B2, 2005/1/5-2025/1/4+584, 申請日:2005/1/5,11/029,587, G06F17/10(2006.01)

12. Chao-Kai Chang, Chia-Chi Chu, and Wu-Shiung Feng, Method of Designing Synchronous Circuit of VLSI for Clock Skew Scheduling and Optimization,," Date of Patent: Jul. 14, 2009,:2006/11/9-2027/3/20: Patent No. US7,562,324B2,2006/11/19, 11/595,151, G12. Chao-Kai Chang, Chia-Chi Chu, and Wu-Shiung Feng, Method of Designing Synchronous Circuit of VLSI for Clock Skew Scheduling and Optimization,," Date of Patent: Jul. 14, 2009,:2006/11/9-2027/3/20: Patent No. US7,562,324B2, 2006/11/19, 11/595,151, G06F17/50(2006.01),2006/11/9-2027/3/20:

13. Hsien-Chin Chiu Wei-Hsien Lee Chien-Cheng Wei Wu-Shiung Feng,

“Manufacturing Method of High-Linearity and High-Power CMOS Structure,” IPC8 Class: AH01L218238FI, USPC Class: 438199

14. Chia-Chi Chu, Ming-Hong Lai, Chao-Hsuan Hsu, and Wu-Shiung Feng, “Method of estimating the signal delay in a VLSI circuit,” US Patent 7600206, Internatinal Class: G06F 17/50, Oct. 6, 2009.

(專利申請中)

1. 李恆哲,何嘉銘,朱家齊,馮武雄, “低耗能超大型積體電路可測性設計之掃描  

   鍊重序方法",程序審查中。092119670

2. 李恆哲,朱家齊,馮武雄,賴銘宏“高速超大型積體電路估測集總RLC 耦合互

  連線路串擾雜訊的方法"申請中華民國專利, 實體審查中。092131727

3. 李恆哲,朱家齊,馮武雄,賴銘宏“一種快速運算含電阻迴路之高速積體電路

   RLC 互連線路系統動差之技巧,"申請中華民國專利, 實體審查中。

4. 馮武雄,李恆哲,朱家齊,何嘉銘, “高速超大型積體電路估測集總RLC 耦合互

  連線路串擾雜訊的方法," 發明, 中華民國, 申請中.

5. 馮武雄,李恆哲,朱家齊,何嘉銘, “低耗能超大型積體電路可測性設計之掃描

   鍊重序方法," 發明, 美國, 申請中.

6. 賴銘宏,馮武雄,張兆凱,朱家齊, “一種同步考慮低時鐘歪曲率及低耗能之時

  鐘樹合成工具," 發明, 中華民國, 申請中.

7. 馮武雄,李恆哲,朱家齊,張兆凱, “一種利用適應性階數多點有理Arnoldi 法

  作簡化電路模型之工具,"發明, 中華民國, 申請中.

8. 馮武雄,李恆哲,朱家齊,賴銘宏, “奈米積體電路中利用遞迴動差法估測非均

   勻性分佈式RLC 耦合互連線路串擾雜訊的驗証方法,"發明,中華民國, 申

   請中.

 

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