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長庚大學 綠色科技研究中心
分類清單
魏一勤

魏一勤

副教授

 

電話

5327

Email

icwey@mail.cgu.edu.tw

實驗室

超大型積體電路實驗室

學歷

  • 國立台灣大學 電子工程 博士

開授課程

103學年度第一學期

  • 硬體描述語言
  • 印刷電路板佈局
    VLSI系統設計

103學年度第二學期
數位積體電路設計

IC設計實驗
專案規劃與管理

專長與研究領域

  • 醫電與VLSI領域
  • Noise-Tolerant Circuits Design
  • VLSI Circuits Design
  • VLSI/DSP Design
  • Low Power VLSI Design
  • Communication-Inspired VLSI Design

簡歷

  • I-Chyn Wey (魏一勤received the B.S. and the M.S. degree from the Department of Electronics Engineering, Chang-Gung University (CGU), Taoyuan, Taiwan, in 2001 and 2003, respectively, and the Ph. D. degree from the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan, in 2008.
    Since Aug. 2008, he joined the faculty of Department of Electrical Engineering, Chang Gung University, Taoyuan, Taiwan, where he is currently an Assistant Professor. His research interests are in noise-tolerant circuits design, VLSI circuits design, VLSI/DSP design, low power VLSI design, and communication-inspired VLSI design.

著作列表

Journal Papers:

1.    I-Chyn Wey, Chien-Chang Peng, and Feng-Yu Liao, “Reliable Low-Power Multiplier Design by Using Fixed-Width Replica Redundancy Block”, accepted in IEEE Transactions on Very Large Scale Integration Systems, 2014. (SCI).

2.    I-Chyn Wey, Tz-Cheng He, Hwang-Cherng Chow, Pie-Hsien Sun, Chien-Chang Peng, “A High-Speed, High Fan-In Dynamic Comparator with Low Transistor Count,” accepted in International Journal of Electronics, 2013. (SCI).

3.    I-Chyn Wey, Yi-Jung Lan, and Chien-Chang Peng, “Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design,” accepted in Microelectronics Reliability, 2013. (SCI).

4.    I-Chyn Wey, and Feng-Yu Liao, “Area-Efficient Fixed-Width Multiplier by Using the Fixed Minor Input Correction Vector”,accepted in International Journal of Electronics, 2013. (SCI).

5.   I-Chyn Wey, Yu-Sheng Yang, Bin-Cheng Wu, and Chien-Chang Peng, “A Low Power-Delay-Product and Robust Isolated-DICE Based SEU-tolerant Latch Circuit Design”, accepted in Microelectronics Journal, 2013. (SCI)

6.    I-Chyn Wey, and Ye-Jhih Shen, “Hardware-Efficient Common-Feedback Markov-Random-Field Probabilistic-based Noise-Tolerant VLSI Circuits”, accepted in Integration, the VLSI Journal, 2013. (SCI)

7.    I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, and Heng-Jui Chou, “Noise-Tolerant Dynamic CMOS Circuits Design by Using True Single-Phase Clock Latching Technique”, accepted in International Journal of Circuit and Theory Applications, 2013. (SCI).

8.   I-Chyn Wey and Chun-Chien Wang, “Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error,” in IEEE Transactions on Very Large Scale Integration Systems, 2012. (SCI).

9.   I-Chyn Wey, Chien-Chang Peng, and Hwang-Cherng Chow, “Wide Bandwidth and High Precision Power Supply Noise Detector by Using Dual Peak Detection Sample and Hold Circuits”, accepted in International Journal of Circuit and Theory Applications, 2012. (SCI). 2

10.   I-Chyn Wey and Shu-Hao Kuo, “All Digital Folded Low-Area, Low-Power Maximum Power Point Tracking Chip for Photovoltaic Energy Conversion System”, accepted in International Journal of Circuit and Theory Applications, 2012. (SCI).

11. I-Chyn Wey, Chien-Chang Peng, Yu-Jiang Liao and Yu-Sheng Yang, “A Precise and Linear Power Supply Noise Detector by Providing a Stable Charging Source,” in IAENG Transactions on Engineering Technologies, pp. 334-346, 2011. (EI).

12.   I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, and An-Yeu (Andy) Wu, “Design and Implementation of Cost-Effective Probabilistically-Based Noise-Tolerant Circuits,” in IEEE Transactions on Circuits and Systems, Part-I, pp. 1211-1224, November 2009 (SCI).

13.  I-Chyn Wey, You-Gang Chen, and An-Yeu (Andy) Wu, “Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits,” in IEEE Transactions on Very Large Scale Integration Systems, accepted 2008 (SCI & EI).

14.  I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, and An-Yeu (Andy) Wu, “Design and Implementation of Cost-Effective Probabilistically-Based Noise-Tolerant Circuits,” Submitting to IEEE Transactions on Very Large Scale Integration Systems (SCI & EI).

Conference Papers:

1.    I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, and An-Yeu (Andy) Wu, “A 2Gb/s High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for SoC Applications,” in Proc. of 2005 IEEE International Symposium on Circuits and Systems(ISCAS 2005), Kobe, Japan, pp. 1074-1077, May 2005.

2.   Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu (Andy) Wu, “A Scalable DCO Design for Portable ADPLL Designs,” in Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, pp. 5449-5452, May 2005.

3.    I-Chyn Wey, You-Gang Chen, Chia-Tsun Wu, Wei Wang, and An-Yeu (Andy) Wu, “A High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for SoC Applications,” in Proc. of 2005 IEEE Ph.D. Research in Microelectronics and Electronics (PRIME 2005), Lausanne, Switzerland, July 2005.

4.    Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu (Andy) Wu, “A Frequency Estimation Algorithm for ADPLL Designs with Two-Cycle Lock-in Time,” in Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos Island, Greece, pp. 4082-4085, May 2006.

5.    Wei Wang, I-Chyn Wey, Chia-Tsun Wu, and An-Yeu (Andy) Wu, “A Portable All-Digital Pulsewidth Control Loop for SOC Applications”, in Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos Island, Greece, pp. 3165-3168, May 2006.

6.    I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu (Andy) Wu,“0.18μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement”, in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), Hangzhou, China, pp. 291-294, Nov. 2006.

7.    You-Gang Chen, I-Chyn Wey, and An-Yeu (Andy) Wu, “A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment”, in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), Hangzhou, China, pp. 295-298, Nov. 2006.

8.    Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, and An-Yeu (Andy) Wu, “Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules,” in Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, pp. 869-872, May 2007.

9.    Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu (Andy) Wu, Hong Zhao, “Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design,” in Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, pp. 1803-1806, May 2007.

10.  Woon Tiong Ang, Hui Fei Rao, Changhong Yu, Jilin Liu, I-Chyn Wey, An-Yeu (Andy) Wu, Hong Zhao, Jie Chen, “A clock-fault tolerant architecture and circuit for reliable nanoelectronics system,In Proc. of 2007 nternational Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), Rabat, Morocco, pp. 186-191, Sep. 2007.

11. Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, and An-Yeu (Andy) Wu, “Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency,” in Proc. of 2007 IEEE Workshop on Signal Processing Systems (SiPS-2007), Shanghai, China, pp. 493-498, Oct. 2007.

12.  I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu (Andy) Wu, “A 0.13μm Hardware-Efficient Probabilistic-Based Noise-Tolerant Circuit Design and Implementation with 24.5dB Noise-Immunity Improvement,” in Proc. of 2007 IEEE Asian Solid-State Circuits Conf. (A-SSCC-2007), Jeju, Korea, pp. 295-298, Nov. 2007.

13.  Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey and An-Yeu (Andy) Wu, “An Efficient Methodology to Evaluate Nanoscale Circuit Fault-tolerance Performance based on Belief Propagation,” accepted by 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, USA, May 2007.

14. I-Chyn Wey and Chun-Chien Wang, “Low-error and Area-efficient Fixed-width Multiplier by Using Minor Input Correction Vector,” in Porc. of IEEE International Conference on Electronics and Information Engineering, Kyoto, Japan, Aug. 2010.

15. I-Chyn Wey, Chien-Chang Peng, Yu-Jiang Liao, and Yu-Sheng Yang, “A Precise Power Supply Noise Detector with High-Linearity,” in Proc. of Workshop on Design, Analysis and Tools for Integrated Circuits and Systems, Hong-Kong, China, Mar. 2011.

16.  I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, “An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term”, IMECS, Hong-Kong, China, March 2012.

17 I-Chyn Wey, Chien-Chang Peng, Wan-Rong Wu, Chao-Chyun Chen, and Chi-Nan Chuang, “High-Performance Noise-Tolerant Markov Random Field Circuit Based on Transmission-Gate Design”, ITC-CSCC, Hokaido, Japan, July 2012.

Patents:

1.    Jie Chen, I-Chyn Wey, Chang-Hong Yu, “Ultra Low Power and Noise Tolerant Circuit Design Methodology,” (Submitting) US, 2007.11.

 

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