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長庚大學 綠色科技研究中心
分類清單
高少谷

 

高少谷

助理教授

 

電話

03-2118800#3198

Email

kaosk@mail.cgu.edu.tw

實驗室

電子電路實驗室

學歷

  • 國立台灣大學    電子工程 博士

經歷

開授課程

103學年度第一學期

  • 電子學(1)
    電子學(3)

103學年度第二學期

電子學(2)

類比積體電路設計導論

專長與研究領域

  • 醫電與VLSI領域/Phase locked loops (PLLs) 、Delay locked loops (DLLs)、Duty cycle corrector (DCC)

簡歷

Shao-Ku Kao received the M.S. in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002 and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2007.
He is currently an Assistant Professor in the department of electrical engineering, Chang Gung University of Taiwan. His research interests include phase locked loops, delay locked loops, duty cycle corrector circuit and mixed-mode clock generator.

著作列表

Journal Papers:

[1]Shao-Ku Kao, Yong-De You,.” Pulsewidth control loop with low control voltage ripple” e, International Journal of  Electronics Letters, 1:4, 168-178, DOI: 10.1080/21681724.2013.85837208 Nov 2013.

[2] Shao-Ku Kao, Fu-Jen Hsieh (2013): A fast-locking PLL with all-digital lockedaid circuit, International Journal of   Electronics, 100:2, 245-258,01 Jun 2012

[3] Shao-Ku Kao, Bo-Jiun Chen, and Shen-Iuan Liu, " A 62.5-625MHz Anti-reset All-digital Delay-locked Loop ", IEEE Trans. Circuits and Systems- II: Express Briefs, vol.54, July 2007.

[4] Shao-Ku Kao and Shen-Iuan Liu, "All-digital Fast-locked Synchronous Duty Cycle Corrector",IEEE Trans. Circuits and Systems- II: Express Briefs, vol.53, Dec. 2006.

[5] Shao-Ku Kao, Shen-Iuan Liu,”All-Digital Clock Deskew Buffer with Variable Duty cycles”, IEICE Trans Electron, vol. 89-C, June 2006

[6] You-Jen Wang, Shao-Ku Kao, and Shen-Iuan Liu,“All-Digital Delay-Locked Loop/Pulsewidth-Control Loop With Adjustable Duty Cycles,”IEEE J. Solid-State Circuits, vol. 41, June 2006.

Conference Papers:

[1]Bo-Jiun Chen, Shao-Ku Kao, Shen-Juan Liu,” An All-digital Duty Cycle Corrector”,VLSI Design, Automation and Test, 2006 International Symposium on, April 2006

 

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